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Robust Mixed-signal Design
in Smart-power IC Processes
R. Gillon
AMI Semiconductors Belgium
ISIE’05 SS8 : Power ICs
Silicon Solutions for the Real World
Smart-power IC’s ?
Analog Control
and Signal Processing :
Inductive
Capacitive
Resistive
Temperature
…
2
Motor
Relay
Lamp
Heat
…
State Machine or
uController based
Transmitters, receivers, protocol engines, …
PowerBUF
handling :
Drivers :
Peripheral Extension
AMUX
State-machine / logic
Vbat to 5V
ROM or
Micro-processor
Regulator
Flash
Memory
: ROM, RAM, EEPROM, OTP
S/H
Sensor Int. :
ADC
PGA
RAM
Communication
interfaces :
HV / LV
Digital Signal Processing
and Control :
DAC
Drivers
HV : transistors, diodes
Temp sense
HV
Sensing
& Control :
ARM7
R8051
OTP
Analogue and
conversion circuitry
Diagnostics
EEPROM
Protections (Flash+RAM)
:
Logic Control
Block
ESD, EMC, over-temperatures, …
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Peripheral Extension
On-board intelligence :
Voltage regulators
Amplifiers, comparators
ADC, DAC
Filters (SC, GMC, RC) …
JTAG
Timer
PWM
GPIO
Comm.
Control
Unit
LIN
Transceiver
LIN
BSD
RS-232
…
Smart-power IC !
Drivers
Analog
Process :
Components
Isolation schemes
Interconnects
PDK :
Logic
Models
Symbols
Pcells
Verification
IP blocks
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Memories
Digital libraries
Analogue blocks
IO's
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Robust Mixed-signal Design
Process :
Components
Isolation schemes
Interconnects
PDK :
Models
Symbols
Pcells
Verification
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How to engineer the design-system
to enable / favour robust design practices ?
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Robust Mixed-signal Design
B. Gilbert in
“Trade-offs in analog Circuit Design” :
…the art of anticipating, identifying and systematically
nulling sensitivities of critical performance
specifications to variances in the manufacturing
process and the circuit's environment
Sources of variability (chip-centric universe) :
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Intrinsic Variations :
inherent to the chip fabrication, the selected architecture
Extrinsic Perturbations :
interaction of the chip with a variable environment
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Intrinsic variations
Process variations
Die-to-die
Intra-die (process-induced gradients)
Component mismatch
Noise
Intrinsic noise (semiconductor physics)
Activity noise (induced ‘random’ signals)
Component aging
Electrical (over-)stress
Temperature gradients
Qualification level (process, components)
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External Perturbations
Better solved by other means …
(than IC design)
Eg : moisture
Not quantifiable, but can be minimized
by appropriate measures during IC design
Eg : Mechanical stress degrading transistor matching
Can be quantified and designed for
Temperature effects
EMC :
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ESD events
Standardised accidental pulses (eg automtive : Shaffner)
Latch-up
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Process Design Kit ?
Netlist
Schematics
Layout
Connect.
Features
Verification
Isolation
Models
CDF
CDF
CDF
CDF
Par.
Symbols CDF
PCells
Analysis
Library
CDF
CDF
Process
Interconnects
CDF
CDF
Compon
CDF
CDF
Comp.
CDF
CDF
Other
CDF
CDF
Conn.
CDF
CDF
IP
CDF
CDF
IP
Components
Components Library
IP Blocks
IP Blocks Library
Analysis scripts
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DRC
LVS
Overview of Robustness Tools
(*) under development
Isolation
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Ext. Perturbations Internal Variations
Process Variation
Interconnects
Components
LVS, XRC
Models
Noise
Models
Aging (*)
Models
Electrical Stress
DRC, LVS, Models
LVS
Schem., LVS, Models
Temp. Gradient (*)
LVS, Models
Qual Level (*)
Ambiant Temp.
ESD
Schem., Models
LVS, Models
Schem., LVS
Models
DRC, LVS
Schem., LVS
Schem., Models
XRC ?
Schem.
Accidental Pulses
EME / EMS (*)
Latch-up (*)
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DRC, LVS
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Schem., Models, Pcells,
Managing Electrical Stress Risks
SYSTEM OF POCKET VOLTAGES :
HV pocket
H HVdifferent
devices
Introducing
voltage ratings
MV pocket
M MV devices
For famillies
nets (through
labelling)
80V
C LV of
device
LV pocket
For diffused pockets (tubs)
FAILURES
20V
Formal management of connectivity of
H1
H3
components, tubs, etc. according to ratings
M4
H
M1nets and pins
M3
DRC rules
C2 on
3.3V
Electrical rule check at schematics level
C1
C3
M2 H2
Safe-operating area flagging during simulation
80V
80V
H
20V
20V
20V
Psub
diode?
M
20V
20V
SUB1
SUB2
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80V
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SUB1
C4
80V
80V
Managing Component Aging Risks
Static approach or guard-banding
The life-times under constant stress are extracted
Models issue safe-operating area messages
according to selected target life-times
Covers most basic needs
140h
10s
1e4s
Forbiddenregion
1y
25y
1e4s
1y
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Managing Component Aging Risks
Static approach or guard-banding
The life-times under constant stress are extracted
Models issue safe-operating area messages
according to selected target life-times
Covers most basic needs
Computation of dynamic aging
Determination of aging rate
Computation of parameter shifts according to age
 it
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d Age I D  I sub 

 
dt
W  ID 
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i
C1  Age n
P

P0 1  C2  Age n
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Managing Process Variations
Die-to-die variations
correlation
matrix
Study distributions of key electrical
parameters
DMOS
spy plot (correlations)
Determine dominant modes of variations
capacitors
MOS
resistors
diode
bipolars
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Id
Id
Id
Managing Process Variations
VTH
vth0
Die-to-die variations
GMmax
u0
Neural
IDsatof key electrical parameters vsat
Study distributions
Network
Ron
R
Determine dominant
modes
of
variations
(correlations)
tox
tox
Vd
Vd
Vd
Identify correlation
groups
E-Test Vectors
Model Par. Vectors
Build sets of corners for each correlation group
Neural Network Training
Alternatively provide process Monte-Carlo models
Measurements
vth0
Modelling
Sensitivityparadox
VTH
u0
Gmmax
Ranking
DOE
Simulations
Statistical data
is available in electrical parameters
vsat
IDsat
R
Ron
ETest parameters
are
not
model
parameters
tox
tox
Model Par.
Vectorsor build special
Either repeat extraction many
times
E-Test Vectors
mapping techniques
Typical Model
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Managing External Perturbations
Electro-Magnetic Compatibility
Standards for Emission and Susceptibility simulations
Typically from low frequency till 1GHz
Dielectric transition frequencies of silicon substrate
Redistribution of current filaments in metals not properly
modelled in most EM simulation tools (avoid to solve electric
and magnetic fields in the conductors).
Need to assess realism of EMC simulations
comparing impedance levels at tip of package lead
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Managing External Perturbations
Testing ESD protection strategy
Smart-power IC’s can have very complex interface
Many different supply levels
IO pins with different voltage ratings
Very large number of pins
Wide variety of ESD protection cells
Tool for testing topology of ESD protection scheme
Drop-in replacement of all component models by simplified
breakdown models
Forcing of static current in IO pins
Detection of current paths through simulation
Flagging of breakdowns outside of ESD protection cells
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Extension to detect risks of dynamic failures
Completed by specific DRC check and generic LVS
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Managing Learning Processes
Road-map for Smart-power technologies
Progressive introduction of new features to meet the
needs and timings of different markets
Consumer
Automotive, Aero, Military
Medical
Several nested feedback loops
Tools to support / channel feedback
Helpdesk systems
Tracking of qualification status at component level
Quality systems : Waivering systems for rule violations, …
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Conclusions
Stimulate robustness by construction
Tackle risks as early as possible in the design process
Favor analytical approaches w.r.t. predefined pushbutton solution
Efficiency and flexibility of solutions is critical
Enabling robustness requires holistic
approach to PDK engineering
ROBUSPIC projects is addressing key topics
in enabling methodologies for robust design
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Acknowledgements
6th framework program (IST) for funding of the
ROBUSPIC program
Partners in ROBUSPIC :
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