Transcript Questa Overview DAC 2005 - Test and Verification Solutions

Industry Trends
Compare and Contrast
Harry Foster
Chief Verification Scientist
State of the Industry
Mindless
Statistics
There are three types of lies - lies, damn lies, and statistics.
-Mark Twain
HDF – HVC 2009
Myth vs. Reality?
HDF – HVC 2009
Slowing Adoption of New Technology
2005
1.72B
Transistors
2004
592M
Transistors
Itanium 2 (9MB cache)
2002
2000
2008
2Billion transistors
Tukwila Quad Core
1999
9.5M+
Transistors
Pentium III
1997
7.5m+
Transistors
1995
5.5M+
Transistors
1993
3.1M+
Transistors
1989
1,290,000
Transistors
1985
1982
1979
29,000
Transistors
Pentium
486
275,000
Transistors
386
134,000
Transistors
286
8088
4
HDF – HVC 2009
Pentium Pro
Pentium II
42M
Transistors
Pentium 4
220M
Transistors
Itanium 2
Dual Core Itanium
Frequent Statements About the Slowing of
Technology Adoption
“The problem is that Moore's Law has
collapsed," he says. Coburn asserts that there
has been a slowdown in the previously steady
move to smaller geometries and larger wafer
sizes.
Pip Coburn, Coburn Ventures
December 15th, 2008
Source: Barron’s “Why it’s going to get a lot worse,” Eric J. Savitz. Dec. 15, 2008
http://online.barrons.com/article/SB122912495865802961.html?mod=gartner
“And, the customers have slowed down or
delayed their technology transitions either by
leveraging their existing installed base or just
by delaying their new product introduction for
later.”
Eric Meurice, Chairman,
President and CEO ASML Holding N.V.
Source: Q4 2008 Earnings Call. January 15, 2009
http://seekingalpha.com/article/115001-asml-holding-n-v-q4-2008-earnings-call-transcript?page=-1
5
HDF – HVC 2009
“The slowdown in process technology
transitions will mean that the
semiconductor industry will be driven
more by economics than technology …”
“You are not seeing these geometries rise
and fall off the way they did before.
Rather, they are living on.”
Len Jelinek, Director and chief analyst,
Semiconductor Manufacturing, for iSuppli
Source: EE Times,“ISuppli: Gear costs to derail Moore's Law in 2014," Dylan McGrath,
June 16, 2009 http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=217900102
Design Completion Trends
Design Completion Share by Linewidth
40%
Percent of Total Design Completions
35%
30%
25%
20%
15%
10%
5%
0%
1993
1994
1995
350nm
1996
1997
250nm
1998
180nm
Source: VLSI Research, Design Completions, September 2008
6
HDF – HVC 2009
1999
2000
2001
130nm
2002
2003
90nm
2004
2005
65nm
2006
2007
2008
45nm
2009
Silicon Volume of Wafer Starts
(in 300mm Wafer Equivalents)
Volume of Wafer Starts by Linewidth (300mm wafer equivalents)
40%
Percent of Total Silicon Demand
35%
30%
25%
20%
15%
10%
5%
0%
1994
1995
1996
350nm
1997
1998
250nm
1999
180nm
Source: VLSI Research, Silicon Demand, EDA Tech Forum June, 2009
7
HDF – HVC 2009
2000
2001
2002
130nm
2003
2004
90nm
2005
2006
65nm
2007
2008
45nm
2009
Reticle Sales Trends
Reticle Revenue Share by Linewidth
40%
Percent of Total Reticle Revenue Share
35%
30%
25%
20%
15%
10%
5%
0%
1993
1994
1995
350nm
1996
1997
250nm
Source: VLSI Research, Reticles, September 2008
8
HDF – HVC 2009
1998
180nm
1999
2000
2001
130nm
2002
2003
2004
90nm
2005
2006
65nm
2007
2008
2009
45nm
Waffer in Production
IC Fab Capacity by Node *
IC Fab Capacity by Node (MSI) January 2004 -to- June 2008
200
IC Fab Capacity (MSI)
150
100
50
0
Jan-04
Jul-04
Jan-05
Jul-05
45nm
Source: VLSI Research, December 15, 2008
9
HDF – HVC 2009
Jan-06
65nm
Jul-06
90nm
Jan-07
130nm
Jul-07
180nm
Jan-08
Jul-08
* Note: Realized
Capacity Utilization Improvement
Favors 65/45nm Technology
100%
180nm
130nm
Capacity by Node - April
90nm
65nm
90%
45nm
80%
70%
>180nm,
27.1%
65nm,
14.7%
50%
180nm,
7.1%
90nm,
19.0%
130nm,
8.6%
150nm,
1.8%
60%
40%
Source: Selantek Capacity Analysis, May, 2009, and October 2009
10
HDF – HVC 2009
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30%
Utilization %
40/45nm,
4.9%
Slowing Adoption of New Technology
Adoption of Leading-Edge Semiconductor
Technology Is at the Same Rate as in the Past
2005
1.72B
Transistors
2004
592M
Transistors
Itanium 2 (9MB cache)
2002
2000
1999
2008
9.5M+
Transistors
2Billion transistors
Tukwila Quad Core
Pentium III
1997
7.5m+
Transistors
1995
5.5M+
Transistors
1993
3.1M+
Transistors
1989
1,290,000
Transistors
1985
1982
1979
29,000
Transistors
Pentium
486
275,000
Transistors
386
134,000
Transistors
286
8088
11
HDF – HVC 2009
Pentium Pro
Pentium II
42M
Transistors
Pentium 4
220M
Transistors
Itanium 2
Dual Core Itanium
Forecast
$ Billions
World Semiconductor Market
80
70
60
50
40
30
20
10
0
62.8 64.7
68.9
62.9 67.3 65.9
52.2
75.1
69.2 72.6
 60% PCs & Cellphones
 Huge growth in smartphones
52.4
43.7
 2013 1/3 cells a smartphones
1Q08
3Q08
1Q09
3Q09
Quarter
1Q10
3Q10
Consumer
Electronics
HDF – HVC 2009
SoC Designs Dominate
HDF – HVC 2009
SOC Design & Verification
Embedded Microprocessor Cores Trend
50%
2004
48%
2007
45%
39%
40%
35%
32%
35%
30%
25%
20%
14%
15%
11%
10%
7% 6%
7%
3%
5%
0%
NONE
1
HDF – HVC 2009
2
3
4
5 or MORE
SOC Design & Verification
Embedded DSP Cores
70%
65%
60%
50%
40%
30%
20%
20%
9%
10%
2%
2%
3%
3
4
5 or MORE
0%
NONE
1
HDF – HVC 2009
2
What Does 45-nm Mean To Us?
Challenges and Opportunities
 Active and standby leakage
accounts for 65% of overall
power consumption at 45-nm
 Low-power techniques are
necessary at 45-nm
 45-nm offers 2X reduction in
die size or 2X increase in gate
count over 65-nm
HDF – HVC 2009
65-nm Conroe
45-nm Wolfdale
300 mm2 45-nm wafer
Myth vs. Reality?
Rising Design Costs Will Limit New Applications
17
HDF – HVC 2009
Transistors Produced per Electrical Engineer
Nearly 4-Orders of Magnitude since 1985
Transistors/Engineer
Total Electronic Engineers
10,000,000,000,000
1,000,000,000,000
Quantity
100,000,000,000
10,000,000,000
1,000,000,000
100,000,000
10,000,000
1,000,000
100,000
10,000
1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007
Source: Technology Research Group – EDA Database, 1986, EDA TAM, 1989 & Gartner/Dataquest 2005 Seat Count Report,
Gary Smith EDA, 2008 Seat Count Analysis VLSI Research, 2008 - Transistors Produced Analysis
18
HDF – HVC 2009
EDA Revenue Is Flat 2% of IC Revenue
EDA License & Maintenance/IC Revenue (% Percent)
4.0%
3.5%
3.0%
2.5%
2.0%
1.5%
1.0%
0.5%
0.0%
1996
1997
1998
1999
Source: Mentor Graphics, EDAC MSS & SIA WSTS
19
HDF – HVC 2009
2000
2001
2002
2003
2004
2005
2006
2007
2008
EDA Cost per Transistor vs
Total IC Revenue per Transistor
1.00E-04
EDA Cost/Transistor ($)
1.00E-05
1.00E-06
1.00E-07
1.00E-08
1.00E-09
1.00E+13
1.00E+14
1.00E+15
Source: SIA, VLSI Research, Federal Reserve
20
HDF – HVC 2009
1.00E+16
1.00E+17
1.00E+18
1.00E+19
1.00E-05
1.00E-06
1.00E-07
IC Revenue/Transistor ($)
ATE Capital Cost/Transistor ($)
1.00E-04
1.00E-08
1.00E-09
1.00E+20
1.00E+13
Note: EDA Cost Consists of EDA License and Maintenance revenue adjusted for Inflation… 1985 - 2007
SOC Design Costs Forecasted to
Exceed $100 Million Within 3 Years
120
100
Impact of Design Technology on SOC Consumer Portable Implementation Cost
$ US Millions
80
60
40
20
0
2007e
2008f
2009f
Hardware Costs
2010f
1
Software Costs
2011f
2012f
2
Notes:
1
2
Source: 2007 ITRS Roadmap
21
HDF – HVC 2009
Total Hardware Engineering Costs + EDA Tool Costs
Total Software Engineering Costs + Electronic Software Design Tool Costs
Software Developers Outnumber
Hardware and Software
of Embedded
WW Population
Hardware
Designers
2-to-1
Developers (units in 000)
(in 000’s)
Hardware
Software
400
350
312
348.3
337.8
325.8
300
250
200
159.5
158.5
157.6
156.6
150
100
50
0
2006
Source: VDC - Embedded Systems Market Statistics 2007
22
HDF – HVC 2009
2007
2008
2009
System Design Has Shifted to the
Semiconductor Suppliers
Apps
Apps
Apps
Apps
Apps
Much of what was part of the endsystem is now incorporated within
a System-On-Chip
Service Abstraction
Middleware
OS
CPU MEM
SW
SW
Driver SW
Driver SW
Driver
Driver
HW
HW
Buses
23
HDF – HVC 2009
HW
HW
Rising Design Costs Limit New Applications
Semiconductor Companies Are Assuming
More of the System and Embedded Software
Engineering Design Responsibility
24
HDF – HVC 2009
Myth vs. Reality?
Verification Is Keeping Up With Moore’s Law
HDF – HVC 2009
An Optimistic View of the Productivity Gap
Let’s assume…
 Number of transistor doubles every 18 months (58% / yr)
 Amount of logic we can design doubles every 2 years (41% / yr)
 Amount of logic we can verify doubles every 2.5 years (25% per year)
Size (# transistors)
Productivity Gap
Verify
Design
Manufacture
Time (years)
HDF – HVC 2009
Productivity Gap
Design Size in Millions of Gates
Verification
Gap
Design
Gap
80
Ability to Fabricate
60
Ability to Design
40
20
0
1988
1992
1996
2000
2005
Ability to Verify
 The Verification Gap
—
Many companies still using 1990’s verification technologies
—
Traditional verification techniques can’t keep up
* Based on data from the 2003 ITRS, Collett International 2004 FV Survey, and customer surveys
27
HDF – HVC 2009
The Verification Gap
Directed Test
State-of-the-Art Verification Circa 1990
 Imagine verifying a car using a directed-test approach
—
Requirement: Fuse will not blow under any normal operation
—
Scenario 1: accelerate to 37 mph, pop in the new
Lady GaGa CD, and turn on the windshield wipers
HDF – HVC 2009
The Verification Gap
Directed Test
State-of-the-Art Verification Circa 1990
 Imagine verifying a car using a directed-test approach
—
Requirement: Fuse will not blow under any normal operation
—
Scenario 1: accelerate to 37 mph, pop in the new
A Few Weeks Later. . . . .
John Mayer CD, and turn on the windshield wipers

HDF – HVC 2009
The Verification Gap
Directed Test
State-of-the-Art Verification Circa 1990
 Imagine verifying a car using a directed-test approach
—
Requirement: Fuse will not blow under any normal operation
—
Scenario 714: accelerate to 48 mph, roll down the window, and turn
on the left-turn signal
HDF – HVC 2009
Concurrency Challenge
 A purely directed-test methodology does not scale
—
Imagine writing a directed test for this scenario!
—
Truly heroic effort—but not practical
HDF – HVC 2009
Today’s Concurrency Challenge
Packet-Based Design
TLP
From
Fabric
Tx
Retry
Memory
DLLP
Rx
From
RX
HDF – HVC 2009
Arbiter
To
PHY
What Are We Doing To Close The Gap?
Size (# transistors)
Productivity Gap
Verify
Design
Manufacture
Time (years)
HDF – HVC 2009
Moore with Less
2005
1.72B
Transistors
2004
592M
Transistors
Itanium 2 (9MB cache)
2002
2000
1999
220M
Transistors
Itanium 2
42M
Transistors
Pentium 4
9.5M+
Transistors
Verification for Every Man, 1997
Woman, and Child in India
Pentium III
7.5m+
Transistors
1995
5.5M+
Transistors
1993
3.1M+
Transistors
1989
1,290,000
Transistors
1985
1982
1979
29,000
Transistors
Pentium
486
275,000
Transistors
386
134,000
Transistors
286
8088
34
HDF – HVC 2009
Pentium Pro
Pentium II
Dual Core Itanium
Myth vs. Reality?
70% of the project effort is spent in verification….
HDF – HVC 2009
Design Engineers Are Becoming
Verification Engineers
Design
54%
Other
14%
Verification
46%
Design
51%
Verification
35%
Source: 2007 Farwest Research IC/ASIC Functional Verification Study, Used with Permission
36
HDF – HVC 2009
More and More Verification Cycles
37
HDF – HVC 2009
Faster Computers
10000.00
1000.00
MIPs
100.00
10.00
1.00
0.10
0.01
1975
1980
38
HDF – HVC 2009
1985
1990
1995
2000
2005
Lots of Computers
25
20
AMD Grid
AMD Grid Growth 2001-2006
(Relative to 2001 = 1.0)
15
10
5
Year
# of Servers
1996
50
2006
5000+
(over 10,000 CPUs)
0
2001
2002
2003
2004
Source: The AMD Grid: Enabling Grid Computing for the Corporation, August 2006
39
HDF – HVC 2009
2005
2006
So, with all this effort, what’s the results?
HDF – HVC 2009
Results
2/3 Projects Miss Schedule
Designs completed on time according to project's original schedule
30.0
25.0
> +10%
20.0
+10%
0
-10%
15.0
-20%
-30%
-40%
-50%
10.0
> -50%
5.0
0.0
> +10%
+10%
Source: 2007 Far West Research and Mentor Graphics
41
HDF – HVC 2009
0
-10%
-20%
-30%
-40%
-50%
> -50%
Results
77% Respins Due to Functional Bugs
2002
45%
40%
35%
2007
39% 42%
38%
39%
33%
28%
30%
Designs
2004
25%
20% 21%
20%
17%
15%
8%
6% 6%
10%
5%
1%
2%
1%
0%
1
2
First Silicon Success
HDF – HVC 2009
3
4
Spins
5
6
>= 7
Source: Collett International 2002, 2004,
Farwest Research 2007 Functional Verification Study
Results
Types of Flaws
2004
2007
100%
80%
75% 77%
60%
40%
33%
24%
32%
26%
23%
21%
20%
0%
20%
22%
19%
19%
27%
27%
25%
14%
17%
15% 13%
11%
LOGIC OR
FUNCTIONAL
CLOCKING
TUNING
ANALOG
CIRCUIT
CROSSTALKPOWER
MIXED-SIGNAL
INDUCED
CONSUMPTION INTERFACE
DELAYS,
GLITCHES
Source: Collett International 2002, 2004,
Farwest Research 2007 Functional Verification Study
HDF – HVC 2009
YIELD OR
RELIABILITY
TIMING – PATH
TOO SLOW
FIRMWARE
11%
TIMING – PATH
TOO FAST,
RACE
CONDITION
7%
IR DROPS
5% 7%
OTHER
Results
Causes of Functional Flaws
70%
60%
60%
50%
41%
40%
35%
30%
18%
20%
15%
10%
3%
0%
INCORRECT or
INCOMPLETE
SPECIFICATION
CHANGES IN
SPECIFICATION
Source: 2007 Far West Research and Mentor Graphics
HDF – HVC 2009
DESIGN ERROR
FLAW IN
INTERNAL
REUSED IP
FLAW IN
EXTERNAL IP
OTHER
Myth vs. Reality?
The industry is evolving its verification capabilities?
HDF – HVC 2009
Productivity Gap
Design Size in Millions of Gates
Verification
Gap
Design
Gap
80
Ability to Fabricate
60
Ability to Design
40
Ability to Adopt?
20
0
1988
1992
1996
2000
2005
Ability to Verify
 The Verification Gap
—
Many companies still using 1990’s verification technologies
—
Traditional verification techniques can’t keep up
* Based on data from the 2003 ITRS, Collett International 2004 FV Survey, and customer surveys
46
HDF – HVC 2009
Dynamic Techniques Usage
67%
FUNCTIONAL SIMULATION AT RTL LEVEL
51%
TIMING SIMULATION AT GATE LEVEL
48%
FUNCTIONAL SIMULATION AT GATE LEVEL
41%
40%
FPGA PROTOTYPING
FUNCTIONAL COVERAGE
37%
36%
33%
ASSERTIONS
FUNCTIONAL SIMULATION ABOVE RTL LEVEL
C/C++ SIMULATION
27%
26%
ANALOG/MIXED-SIGNAL SIMULATION
HARDWARE/SOFTWARE CO-VERIFICATION
25%
24%
23%
SYSTEM C SIMULATION
TRANSISTOR-LEVEL SIMULATION
TRANSACTION-LEVEL SIMULATION
21%
EMBEDDED CHECKERS TO TRAP ILLEGAL CONDITIONS IN THE DESIGN
EMULATION (COMMERCIAL SYSTEMS)
ACCELERATED SIMULATION
EMULATION (CUSTOM BUILT SYSTEMS)
RF SIMULATION
PROTOTYPING WITH SPECIAL TEST CHIPS
0%
Source: 2007 Far West Research and Mentor Graphics
HDF – HVC 2009
10%
10%
10%
9%
7%
20%
40%
60%
80%
100%
Static Verification Techniques Usage
83%
STATIC TIMING ANALYSIS
EQUIVALENCE CHECKING AT GATE
LEVEL
62%
57%
CODE REVIEWS
48%
CODE COVERAGE ANALYSIS
CODING GUIDELINES THAT ARE
ENFORCED
44%
43%
LINT CHECK
EQUIVALENCE CHECKING ABOVE GATE
LEVEL
40%
35%
DESIGN FOR VERIFICATION TECHNIQUES
19%
FORMAL PROPERTY CHECKING
Other
1%
0%
Source: 2007 Far West Research and Mentor Graphics
HDF – HVC 2009
20%
40%
60%
80%
100%
Stop, time to recap. . . .
49
HDF – HVC 2009
Recap
1. Industry fails to mature its processes
2. Concurrency is difficult to verify
3. Throw lots of bodies at the problem
4. Throw lots of computers at it too
5. All this . . . and poor results
HDF – HVC 2009
Verification Challenges Keep Coming
 Low power
 Clock domain crossing
 Hardware/software
 Network-on-chip
 Multi-level verification
 Multi-core verification
 System verification
 IP reuse (black box)
 Mixed-signal (RF/analog/digital)
51
WCR–February,
2008
HDF
HVC 2009
Myth vs. Reality?
The biggest bottleneck in the flow is simulation performance?
HDF – HVC 2009
Debugging is the Bottleneck
Effort Allocation of Dedicated Verification
Engineers by Type of Activity
34%
52%
14%
Verification Debug
HDF – HVC 2009
Testbench Development
Other
Hey. . . how about some possibilities
and prescription!
HDF – HVC 2009
SoC Designs Dominate
Coverage Confusion
Coverage — How big of a deal is it?
HDF – HVC 2009
Coverage Confusion
How big of deal is it?
Confused
Not A
Problem!
Major
Deal!
Coverage Adoption
100%
90%
80%
70%
60%
50%
48%
40%
40%
30%
20%
10%
0%
CODE COVERAGE
HDF – HVC 2009
FUNCTIONAL
COVERAGE
Challenges Users Want Solved
3 of the top 6 changes are related to coverage!
Other
2%
CREATING FUNCTIONAL
COVERAGE MODEL
9%
TIME TO DISCOVER THE
NEXT BUG
9%
10%
ISOLATING BUGS
MANAGING THE
VERIFICATION PROCESS
15%
MANAGING COVERAGE
DATA
18%
38%
CLOSING COVERAGE
0%
5%
HDF – HVC 2009
10%
15%
20%
25%
30%
35%
40%
Summary
 Today I shared some common themes and insight of
what we are seeing and hearing in the industry
HDF – HVC 2009
59
WCR–February,
2008
HDF
HVC 2009