Transcript Damerell

A Silicon Pixel Tracker (SPT) for ILC/CLIC
Chris Damerell (RAL)
CONTENTS
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For overview, refer to SiLC Collab Mtg in Paris, January 2010
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Brief reminder of goals, design principles and suggested architecture
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Feasibility – new results with charge-coupled CMOS pixels from Jim Janesick
(California) and e2V (Chelmsford) working with Tower/Jazz Semiconductors
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Further exciting information will be reported from the Fairchild/Andor/PCO collaboration
(‘sCMOS’ devices) by G Holst at Pixel-2010 workshop in Grindelwald next month
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Reminder
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Thin monolithic pixel detectors, to be specific charge-coupled CMOS pixels look
promising for an ultra-low mass SPT for ILC or CLIC
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The largest pixel tracking system in HEP (the SLD vertex detector with 307 Mpixels) used
CCDs. Charge-coupled CMOS pixels have evolved from this technology, but achieve
higher functionality by in-pixel and chip-edge signal processing
•
Key features required for SPT are timing at the 10 ns level (for timing layers) and onsensor data sparsification (for both timing and tracking layers)
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By keeping to the simple monolithic planar architecture (pure CMOS technology) the
systems will be easily scalable to the level of ~30 Gpixels for both timing and tracking
layers.
•
This may eventually be true for more complex architectures (eg vertical integration or
3D). However, on grounds of simplicity and minimal cost, we seem to have in hand an
attractive solution …
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Regarding the design concept, many thanks to ILD and SiD colleagues for helpful
suggestions since Sendai workshop, March 2008. Official UK position is that work has
been entirely shut down since December 2007!
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Updated layout (March 2010)
Timing layers, 3 outer
and 1 or 2 inner
Tracking sensor,
one of 11,000,
8x8 cm2,
2.56 Mpixels each
5 tracking endcaps, only
one shown
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Barrels: SiC foam ladders, linked mechanically to one another along their length
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Tracking layers: 5 closed cylinders (incl endcaps) ~50 mm square pixels
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~0.6% X0 per layer, 3.0% X0 total, over full polar angle range, plus <1% X0 from VXD
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Timing layers: 3 as an envelope for general track finding, and one or two between VXD
and tracker, ~1.5% X0 per layer, evaporative CO2 cooling ~150 mm square pixels
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Matching endcap layers: 5 tracking and 3 timing (envelope)
• Both sensor types use charge coupled CMOS architecture, high resistivity Si thinned to ~30 mm, active
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over full area apart from ~3 mm along one edge, tiled in azimuth to exclude dead regions in any layer
Track reconstruction
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Start with mini-vectors from on-time tracks seen in the timing layers, together with an
approximate IP constraint
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Work inwards through each successive tracking layer, refining the track parameters as
points are added
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For curlers at polar angles near 90 degrees, timing information from the endcap layers
will be less useful; recover by using the relatively short inner timing barrel
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K-shorts and lambdas should be findable, starting from the mini-vectors in the timing
layers, omitting the IP constraint and substituting a V0 constraint
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Background level (~7000 out-of-time tracks at CLIC at 3 TeV) appears daunting, but pixel
systems can absorb a very high density of background without loss of performance
(ACCMOR, SLD)
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Very back-of-envelope calculations (LCWS Warsaw); looking forward to a real simulation
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Can if necessary make system more robust, for example by switching some of the
endcap tracking layers to timing, at cost of ~0.9% X0 per layer
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By reading out steadily between trains, we avoid the mechanical and thermal issues of
pulsed power. Tracking layers can be comfortably handled by a gentle flow of cooling
gas (hence minimising the material budget); timing layers will need active cooling such
5th evaporative
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as
CO2
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General principle, established in ACCMOR and SLD vertex detectors – granularity can to
a great extent compensate for coarser timing. Precision time stamping costs power,
hence layer thickness, fine granularity need not
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Technical challenges:
• 30 Gpixels for tracking layers. Reasonable, given progress in astronomy etc
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Excellent charge collection efficiency with large pixels, and few-e- noise
performance from large area devices, due to small signals from thin layers. Now
achievable with charge-coupled CMOS pixel technology
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Fast charge collection (<10 ns for CLIC, ~100 ns for ILC) for timing layers
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New results for Jim Janesick, reported at workshop on imaging systems for
astronomy, San Diego, June 2010
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LSST R&D going well – final stages of prototyping
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SPT tracking layers for ILC or CLIC
Photogate patterned implants
(Goji Etoh)
readout
transfer gate
p-shield
SPT pixels (~50 mm diameter):
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PG preferred over PPD for such large pixels, charge collected under the ring-shaped transfer
gate and then to the gate of one of 3 tiny transistors, below the p-shield
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Very promising also for timing layers (with additional in-pixel logic): Goji Etoh’s patterned
implants – all signal charge can be collected with time spread of ~ 10 ns
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Following figures from Janesick SPIE 7742-11 (to be published)
4 x 4 cm square devices in Sandbox 6 (SB 6), 10 x 10 cm to be processed next
year, in SB 7. SB 6 yields are ‘high’
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RTS noise
Janesick 2006
Janesick 2006
Note: These fluctuations amount to only
0.3% of the drain current
•
RTS is the dominant residual noise source in charge-coupled CMOS pixels
• As with CCDs, transistor noise can be much reduced by using a buriedchannel MOSFET for the source follower (but not completely eliminated, due to
the presence of bulk traps). Now established for CMOS pixels by recent work
from Janesick …
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Responsivity can be reduced by switching in
extra node capacitance – currently by external
control, potentially by in-pixel logic. Long
discussed, now working beautifully
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For SPT, would process on
say 35 mm thick epi, then thin
wafers to ~30 mm for assembly
onto ladders
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Goji Etoh, 2009
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90% charge collection from
uniform illumination of back
surface within ~5 ns
(simulation)
Goji Etoh, 2009
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backup
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End view of 2 barrel ladders (‘spiral’ geometry)
SiC foam, 4-8%
wedge links at ~40 cm
intervals
**
Sensor active width 8 cm,
with ~2 mm overlaps in rf
devices will be 2-side
buttable, so inactive
regions in z will be
~ .2 mm ( ~ 0.2%)
thin Cu/kapton tab (flexible for
stress relief), wire bonds to
sensor
Sensor thickness ~100 mm,
inner 30 mm active
** single layer Cu/kapton stripline runs length of ladder, double layer in region
of tabs (~5 mm wide) which contact each sensor. Single Cu/kapton stripline
runs round the end of each barrel, servicing all ladders of that barrel
Bottom line: potential material budget ~0.6% X0 per layer, but much design
and R&D needed to establish mechanical stability, including shape stability
wrt push-pull operations (taking advantage of stress-free 3-point kinematic
mount)
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SPT timing layers for ILC or CLIC
Regions where full time stamping is needed – 300ns or 10 ns
transfer gate
readout
p-shield
SPT pixels (~50 mm diameter):
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in-pixel discriminator and time stamp for binary readout, possibly with multi-hit register
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Between bunch trains, apply data-driven readout of hit patterns for all bunches separately
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p-shield ensures full min-I efficiency, even if a large fraction of the pixel area were to be
occupied by CMOS electronics
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Disadvantage: the power dissipation per unit area, and impact on layer thickness
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