Transcript Digital Logic Design

Digital Logic Design
Lecture # 9
University of Tehran
Outline
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MSI Parts as a Decoder
Multiplexer
Three State Buffer
MSI Parts as a Multiplexer
Realization of Switching Functions Using
Multiplexers
MSI Parts as a Decoder
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
Up till now, we saw a modular component named as
a decoder. Let’s now see what standard modules
with that functionality are available.
74138: This standard decoder is the most used in
between the MSI decoders. It has active-low
outputs, and one of the enable inputs is also activelow, while the other two are active-high. There is no
particular reason to why they are 3 enable inputs
other than obeying the standard number of pins
these packages have.
74138
Y0N
Y1N
Y2N
Y3N
Y4N
Y5N
Y6N
Y7N
3:8 DECODER
A
B
C
G1
G2AN
G2BN
1
MSI Parts as a Decoder
(continued…)

74154: As in the 74138, this package also needs
activity of both enable pins to work.
74154
A
B
C
D
G1N
G2N
2
O0N
O1N
O2N
O3N
O4N
O5N
O6N
O7N
O8N
O9N
O10N
O11N
O12N
O13N
O14N
O15N
DECODER
MSI Parts as a Decoder
(continued…)

74139: This decoder is often called a dual 2-to-4
decoder and is actually just two 2-to-4 decoders in
one chip.
74139
A1
B1
A2
B2
G1N
G2N
3
Y10N
Y11N
Y12N
Y13N
Y20N
Y21N
Y22N
Y23N
2:4 DECODER
Multiplexer
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Data is stored as bytes in computer memory. When
discussing data transport, a lot of wiring would be
needed to be able to move 8 bits of a byte in parallel.
Trading cost for performance we use serial
connections to transport one bit of data at a time.
This means we share a transition line between the
source and destination.
Multiplexer (continued…)

For instance, in the following diagram, the transition
line works of 1ms between A and A’ and then changes
position as the next bit move on. In this diagram the
first box is a multiplexer and the second a
demultiplexer. The multiplexers we discuss have no
memory.
Multiplexer
A
B
C
D
Demultiplexer
A’
B’
C’
D’
Multiplexer (continued…)

Let us consider such a module with one output and
four inputs, where one of the four inputs must be
selected for output through 2 selection lines.
MUX
I0
I1
I2
I3
y
S1
S0
S1
0
S0 y
0 I0
0
1
1
1 I1
0 I2
1 I3
Multiplexer (continued…)

To observe the gate level design of such structures,
let’s consider a dual 4-to-1 MUX and show its design:
S1
S1
S0 } 0/3
S0
1I0
1en
1en
1I0
1I1
1I2
1I3
2en
2I0
2I1
2I2
2I3
1I1
1y
1I2
1y
1I3
2I0
2en
2I1
2y
2I2
2I3
2y
Multiplexer (continued…)

We need to be able to construct larger multiplexer
modules by cascading smaller ones. This cascading
is done by using the enable inputs of our smaller
modules as shown in the following figure:
S2
S1
S0
S1
S0 } 0/3
a
b
c
d
1en
1I0
1I1
1I2
1I3
1y
y
e
f
g
h
2en
2I0
2I1
2I2
2I3
2y
Multiplexer (continued…)
y1

Recall the
structure can be used as a 1y
to-2 decoder which has been used to choose the
particular 4-to-1 MUX to be enabled in the last
example. That is when s2=0 the upper package is
working and when s2=1 the lower one. We could
have used a 2-to-1 MUX to choose between 1y and
2y and use s2 as the selector.
0
Multiplexer (continued…)

Let’s observe different structures of a 2-to-1 MUX:
s
s
I1
6
4
I1
6
I0
6
4
y
y
4
I0
1
2
Multiplexer (continued…)

About the second structure as a MUX shown in the
last slide it must be mentioned that it would have
been logically correct use a PMOS transistor instead
of the inverter and NMOS, but PMOS transistors are
much slower than the same size NMOS transistors, so
this structure is preferred (this structure uses the
level before as its power supply).
Multiplexer (continued…)

Multiplexers can be used in the design of both
complex circuits and also realization of primitive
gates such as XOR and AND gates.
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XOR gate: If we look at an XOR gate’s functionality a little
differently, we can easily see that when one input is 0 the
other is simply propagated through and when one is 1 the
other is complemented. Using a multiplexer to realize this,
is shown in the following figure. This realization uses only 6
transistors if we use the second method used for a 2-to-1
MUX whereas XOR gates usually consist of 8 transistors.
a
b y
0
0
1
1
0
1
0
1
0
1
1
0
a
b
0
y
-
b
1
Multiplexer (continued…)

AND gate: Again we use only 4 transistors instead of the
usual 6 used for an AND gate.
a
0
0
y
b
1
a
b y
0
0
1
1
0
1
0
1
0
0
0
1
Three State Buffer
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
Another useful and primitive component in digital
circuits is the three state buffer:
c
a y
0
0
1
1
0
1
0
1
Z
Z
0
1
c(control)
ENB
y(output)
a(input)
This three state buffer lets it’s input through to the
output when the control is 1 and give a high
impedance output otherwise.
Three State Buffer
(continued…)

Different three state buffers that are used, are listed
below:
ENB
ENB
buff if 1
ENB
ENB
buff if 0
not if 1
not if 0
Three State Buffer
(continued…)

Let us know use our knowledge of three state buffers
to construct other structures that realize multiplexers
and observe some new concepts. Thus for a 4-to-1
MUX, we have:
I
ENB
0
I1
ENB
I2
ENB
I3
ENB
en
0
1
y0
y1
y2
y3
Three State Buffer
(continued…)


Note: It must be taken to consideration that a wired
OR structure can only be used when we have three
state lines.
We can do cascading on packages with three state
outputs with the same type of ORing:
a
b
c
d
en
I0
I1
I2
I3
y
S1
e
f
g
h
en
I0
I1
I2
I3
y
S1
S2 S1 S0
S0
S0
Shows three
state outputs
MSI Parts as a Multiplexer
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
Let us now see some standard multiplexer packages.
74153: It’s clear that this package is a dual 4-to-1
multiplexer.
74153
A
B
1GN
1C0
1C1
1C2
1C3
2GN
2C0
2C1
2C2
2C3
1
1Y
2Y
MULTIPLEXER
MSI Parts as a Multiplexer
(continued…)

74157: This is a quad 2-to-1 MUX with common
select and enable inputs. Outputs are not in three
state.
74157
SEL
A1
B1
A2
B2
A3
B3
A4
B4
GN
2
Y1
Y2
Y3
Y4
MULTIPLEXER
MSI Parts as a Multiplexer
(continued…)

74251: This is an 8-to-1 MUX that gives us the
complemented form of the output too. The outputs
are three state and the last level of the MUX can be
seen below:
74251
3
WN
ENB
Y
MULTIPLEXER
y
...
GN
D0
D1
D2
D3
D4
D5
D6
D7
A
B
C
WN
MSI Parts as a Multiplexer
(continued…)

Note:
ENB
Realization of Switching
Functions Using Multiplexers

Multiplexers can also be used to realize more
complex switching functions, for example we will now
realize a full adder using a 74153 multiplexer module.
a
cin
b
F . A.
sum
cout
a
0
0
b
0
0
cin
0
1
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
1
0
1
co
0
S
0
0
1
1
1
0
1
0
1
0
0
1
1
0
1
Realization of Switching Functions
Using Multiplexers (continued…)
ab
cin
0
01
11
10
0
1
0
1
0
2
1
6
1
0
3
7
cin
cin
cin
cin
0
5
cin
00
01
11
0
0
1
2
0
1
0
S
0
1
4
1
1
ab
0
00
6
1
3
cin
10
0
4
1
1
7
1
5
cin
co
Realization of Switching Functions
Using Multiplexers (continued…)
a
b
cin
cin
0
cin
1
0
1
} 0/3
en
0
1
2
3
S
en
0
1
2
3
co