Transcript Luisa_Pirozzi_6-12

Crystalline Silicon Solar Cells:
from the Material to the Devices
Luisa Pirozzi
ENEA c-Si PV labs
[email protected]
-
-
ENEA Crystalline Si PV laboratory – Rome
http://wwwcas.casaccia.enea.it/sicri/
I
-Introduction
-Cell Design
-Silicon technology
II
-Cell fabrication processes
-Crystalline Silicon Solar Cells
1839 (Becquerel): lightdependent voltage between
electrodes immersed in an
electrolyte
1941: first Silicon solar cell
(announced in 1954)
1958: first space applications
PV cell structure:
• p-n junction with
upper electrode shaped
as a grid to allow light
(photons) transmission
SUNLIGHT
FRONT CONTACT
(GRID)
ANTIREFLECTIVE
COATING
N - REGION
LOAD
DEPLETION
LAYER
P - REGION
_+
_+
_+
BACK CONTACT
• incident photons having energy higher than the band gap of the
semiconductor are absorbed in the material generating electron and
hole pairs
• carriers created at distance less than the diffusion lenght from the
depletion layer are separated by the electric field there existing and a
potential difference arises across the junction
• if the device is connected to a load the photoinduced voltage allows a
current flow in the load
Energy
distribution
(W/m2 / mm)
2000
nh - Eg
1000
net energy
nh < Eg
0.3
1.1
Spectral distribution of sunlight
wavelength l (mm)
2.5
35
30
GaAs
Single crystalline Si
24,7%
25
Eff (%)
20
Multicrystalline-Si 19,8%
15
10
5
0
0
0,5
1
1,5
2
2,5
3
3,5
Eg (eV)
As for IC, Silicon is not the best material for solar cells:
band-gap too narrow and low absorption coefficient (indirect gap)
4
1E+02
1E+06
1E+01
1E+05
1E+00
1E+04
1E-01
1E+03
1E-02
1E+02
1E-03
1E+01
1E-04
1E+00
1E-05
1E-01
1E-06
1E-02
500 600
700
800
1E-07
900 1000 1100 1200
Wavelength (nm)
ARC
REGION P
REGION N
400
GRID
300
Absorption Depth (cm)
Absorption Coefficienct
-1
(cm )
1E+07
  q(V  Rs I  
I(V)  I L  I 0 exp 
 1

  nkT  
IL=photogenerated current
I0=diode saturation current
q=electron charge
Rs=series resistance
n=diode ideality factor (1 - 2)
k=Boltzmann’s constant
I
PV CELL PARAMETERS
Isc
Im
Isc =short circuit current
Voc=open circuit voltage
Pm=maximum power output= Vm Im
FF=Fill Factor=Pm / Isc * Voc
P m = V m Im
h =efficiency =Pm / Pin= Voc IscFF/ Pin
Pin=total power of incident light
V
Vm
I sc  I L
Voc 
Voc
nkT  I L 
ln 
q
 I0 
 qV 
ln 1  m   1
nkT 
FF  1  
ln (I L / I 0 
Amp.
Amp.
4
4
I1 = 1 kW/m2
3
3
T1 = 20°C
2
2
I2 = 0,5 kW/m2
1
1
T2 = 60°C
0
0,0
0,2
0,4
0,6
Volt
I-V curves at different light
Intensities
0,8
0
0,0
0,2
0,4
0,6
I-V curves at different
Temperatures
Volt
0,8
-Cell Design
- the cell design must take into account
its application:
Production-terrestrial, space,
concentration, architecture, etc
Lab- high efficiency, theoretical limit
-process lay-out:
from three to more than 20 steps
production line –clean room
-Si cells theoretical efficiency
limit: 27%
-Record efficiency: 24.7%
- Average efficiency
(production): 14.5%
Cell Parameters
•Jsc- short circuit current
 optical absorption
 base recombination (red light)
 emitter recombination (blue light)
•Voc- open circuit voltage
 bulk recombination (Job)
 emitter recombination (Joe)
Space charge region (Jor)
•Fill Factor
Ideality factor (n)
Series resistance (Rs)
Shunt resistance (Rsh)
To optimise cell efficiency:
-Increase carriers
generation
-Increase carriers
collection
Losses: recombination, resistive
Recombination:
Joe:
Jr:
Job:
Front surface
Emitter
space charge region
Base
Back
Resistive:
Bulk
Emitter
Back
Contact grid
Shunt
Crystalline Silicon
• over 90% of world-wide solar cell production
(1400 MW in 2005)
- Second most abundant element
- Only semiconductor employed in microelectronic
industry
Large-scale production/Technology coming from
microelectronics
-Silicon technology
Silicon is the second most abundant element, but about half of
the cell cost is due to the substrate.
Silicon production steps:
1) From sand to metallurgical-grade Silicon (MG-Si)
2) MG-Si to semiconductor-grade Silicon (SeG-Si)
3) Crystal growth
Solar grade silicon
“sand”
coke
HCl
UMG-Si
Fluid bed
Reactor
Arc Furnace
SiHCl3
Siemens
poly
Ingots for electronics
Process
Low
quality
Scraps
60 $/kg
15 - 30$/kg
1-2 $/kg
Single crystal
Multi crystal
Silicon
Metallurgical-grade Silicon (MG-Si)
-
Due to the relative impurity of sand, quartzite – 99% SiO2- is the
starting material.
-
Silicon is produced in an Arc Furnace, at T about 1900°C, reducing
SiO2 by Carbon ( coke, coal and wood chips):
SiO2 + 2C
Si + 2 CO
Liquid silicon is poured into shallow troughs.
MG-Si 98% pure (major impurities Fe and Al).
Cost 1-2$/Kg
Metallurgical-grade Silicon (MG-Si)
Semiconductor grade Si (SeG-Si)
For use in electronics, impurities must be almost completely removed
MG-Si purification (Siemens process)
MG-Si is converted to a volatile compound
Si + 3HCl = SiHCl3 + H2
Trichlorosilane is produced by multiple fractional distillation
SeG-Si is obtained reducing Trichlorosilane by H2:
SiHCl3 + H2 = Si + 3HCl
Result: polysilicon
Crystal Growth
-Silicon for electronic industry
must be not only impurity-free,
but also a single crystal, defectfree.
-Poly-Si is molten and grown
into single-crystal ingots:
Czochralsky (CZ)
Floating Zone (FZ)
Czochralsky (CZ) method
-SeG polycrystalline Si is molten in a
crucible, at T=1410 °C
-A crystal seed is dipped into the molten
Si and pulled slowly out of the melt in
the vertical direction while rotating:
crystallization at solid/liquid interface
- SeG- Si residual impurities are
confined in liquid phase
- dopants (B, P) can be added to the melt
- Ld=200 mm t15 msec
-A zone of molten Si is
slowly passed along the
length of a poly-Si ingot.
Floating Zone (FZ) Method
-Material melts at one
boudary and recrystallizes at
the other.
-High purity regrown Si
crystal: no crucible, liquid
region prevents impurity from
entering the growing crystal
-Ld>500 mm t>100 msec
•Microelectronics
•Photovoltaic
1 Si wafer for
1 Si wafer for
>106 chips
1,5Wp; 1,5KWh/year
•PV application requirements much less severe than in electronics:
-impurity levels
-carriers transport properties
•Silicon especially developed for PV:
Multi-crystalline Si
Ribbon
Solar grade Si
Multi-crystalline Si
-Crystalline grains random oriented.
-Grain boundaries: recombination
centers - shunt paths for current.
-Columnar structures and large grains
(some mm): comparable to single-crystal
Ld>150 mm t>10 msec
-Production less expensive
-55% Si cells production on mc-Si
(record EFF: 19,8%)
Multi-crystalline Silicon
Casting
-starting material: scraps of
ingots for microelectronics,
molten in a quartz crucible.
- DS method:
Solidification starts from the
bottom: columnar ingot growth.
Ld 200 mm t >10 msec
Ribbon
- Almost half of the material is
lost during wafering.
•Silicon is grown in ribbons
(250-300 mm)
-EFG method (Edge-definedFilm-fed-Growth):
Molten Silicon moves up the
interior of a grafite die by
capillarity.
Solar grade Silicon
-some metallic impurities
can be present in
concentrations>1015/cm3
(100 times > SeG-Si)
hN
-Preparation of Silane
(SiH4) from metallurgical
grade Si
-Deposition of Si from
SiH4
at/cm3
-Cell fabrication processes
Emitter formation
Ohmic Contacts
Anti Reflection treatments
Emitter
•photogeneration in blue region of
spectrum
•collection of photogenerated carriers
shallow, lightly doped, passivated (low
recombination)
•Contribution to Series Resistance:
deep, heavily doped
•Compromise: junction profile
GRID
REGION N
REGION P
ARC
n/p Junction
n type
(donors)
p type
(acceptors)
Phosphorus
Boron
Arsenic
Aluminum
Antimony
Gallium
-thermal diffusion of dopant atoms into
the silicon (p doped during growth)
Phosphorous thermal Diffusion in Silicon
Solid
Diffusion source:
Liquid
Gaseous
Doped Oxide, spin-on, screen
printing, thin films
laser
Open tube
-Phosphorus: most used
Fick laws: I) J= -D grad C II) C/ t = D 2C/ x2
J = flux
C = concentration
Exhaust
POCl3 25 ºC
Quartz tube
Quartz
Thermostat
Mass flowmeters
O2
N2p
N2
Reactive Gas
Carrier Gas
Carrier Gas
“open tube” diffusion:
a) Predeposition on wafer surface
b) Drive-in: P atoms diffusion
T: 800-1000 °C; N2 and O2
Silicon Wafers
Source: POCl3
2POCl3 + 3/2O2  P2 O5+3 Cl2
Si + O2  SiO2
5Si + 2P2 O5  5SiO2 +4P
SiO2 : better control of diffusion process
•Temperature, time
duration and dopant
source determine:
-P surface concentration,Cs
-xj=junction depth
-resistance and t of
diffused region
- when Cs > P solubility
limit (1021 at/cm3 a 1000ºC)
dead layer: high defect
density region , low t
-Concentration profile:
C(x,t)=Cs erfc(x/2Dt)
D= D0 exp (-E/KT) P diffusion coefficient in Si
(10-14 cm2/sec a 980 ºC)
Laser Assisted Doping
laser beam creates dopant atoms (PCl3 pyrolysis or solid source) and
simultaneously induces melting of silicon:
dopant liquid phase diffusion.
Localized process, low thermal budget
Fast diffusion kinetics
PCl3
P
P
P
p - Si
P
+
n
P
P
p - Si
TEM picture of laser
doped silicon after recrystallization
Dopant concentration profile
Surface Passivation
•Surface: critical discontinuity in the
crystal structure
-High density of allowed states within
the forbidden gap
•Silicon: surface-state density reduced
growing passivating oxide
-interface between oxide and Si moves
towards bulk
0.8
Y Axis Title
•Thermal Oxidation: open tube, in O2
at T 800-1000 °C
1.0
0.6
B sel23ox
0.4
D sel23
E om 23
0.2
F sel23+om 96
0.0
400
•low T alternative: SiN layer
600
800
X axis title
1000
1200
Ohmic Contacts
-Front contact must minimize series
resistance losses, providing at the same
time the maximum light amount to reach
the cell surface.
-A good back contact allows to increase
Jsc and Voc (confinement techniques).
-Good ohmic contact metal/silicon
-Low metal resistivity
Ohmic Contacts
Front Grid:
-Busbar are directly connected to the external load
-Fingers collect current to delivery to a busbar.
Rs=Rbase+Remitter+Rgrid
Contact technologies
- photolitography
vacuum
evaporation
-screen printing
- electrochemical
growth
Deposition
technique/
Metal
Electro-plating
Electroless
Evaporation
Ni
Front
Front
Au
F/B
F/B
F/B
Ag
Front
Front
Front
Ti
Front
Pd
Front
Al
Back
Back
Screen printing
Back
-Schottky barrier
High contact resistance
Metal/Si contact
-ohmic contact is obtained by
reducing barrier width:
tunneling
- high P concentration at Si
surface can reduce barrier
width:
Highly doped emitters
Alloying
Annealing at T 450-800 °C
metal
Silicon
Photolitography
- photosensitive polymer is deposited on wafer
surface
-Regions to metallize are exposed through a mask to
UV light
- Vacuum evaporation
Front:
Ti (400 A) adherence to Si
Pd (200 A) barrier layer
Ag 1-5 mm good conductivity
Back:
Al 1mm
-Lift-off: photoresist removed in acetone
-Annealing: 400- 600 °C N2 or forming gas
ohmic contact
Resolution: few microns
Shadowing < 4%
Screen printing
-contact grid is obtained by depositing on
wafer surface, through metal screens, inks or
conductive pastes
-inks contain metal grains (Ag, Al), glasses,
organic binders and solvent
1000
900
800
700
Temperatura (°C)
-Firing:
In a belt furnace, the glass melting
temperature (about 800°C) is reached for
few minutes
Contact to Si: alloy metal/Si (Al) through
glass matrix (Ag)
•Resolution: 80-100 micron
Shadowing:10%
600
500
400
300
200
100
0
0
10
20
30
40
Tempo (s)
50
60
70
Selective Emitter
•Heavy doped emitter :
low response in blue region “dead layer”, photogenerated
carriers have low probability to
be collected•Selective emitter:
regions under contacts are
heavy doped, to reduce Rc
Exposed region is low doped to
increase collection in blue
spectral portion
- double diffusion, laser doping
(a)
(b)
Back Surface Field
Si
Si
Al/Si-liquid
Al-layer
Seff
Sf
T=25C
(c)
p-Si
T> 577C
p
p+
e-
p
(d)
n+
Bulk
BSF
EF
p-Si
Emitter
p+-Si
p+-Si
Al/Si-liquid
Al/Si-layer
577C
T 577C
cooling
T>
cooling
Sb
Wb
WBSF
AntiReflection treatments
•Silicon reflects 35% of
incident light, and up to 54% at
short l (high refractive index n)
•Techniques to reduce losses:
-Deposition of one or more
layers of thin oxides
- Surface Texturization
Thin AR layers
•losses due to reflection can be drastically reduced
r12  r 2 2  2r1r 2 cos 2
R
1  r12 r 2 2  r1r 2 cos 2
 n 0  n1 
r1  

n
0

n
1


R  Rmin
Rmin
2
 2n1d 1 

 l 
 n1  n 2 
r2  

 n1  n 2 
 
 l0 
n1d 1   
 4
 l0 
d1  

 4n1 
 n1  n0n 2 
 2

 n1  n0n 2 
2
 n 2  n0 
R

 n 2  n0 
2
R min  0
n1  n0n 2
Thin AR layers
• single layer AR coating:
l0= 600 nm; n1=2.0; d1=750 A
•Losses reduced to 10%
Material
n
Si
3,45
SiO
1,9
Al2O3
1,9
Si3N4
2,0
TiO2
2,2
Ta2O5
2,2
Double layer AR coatings
-better match between
high index of Si (3,5) and
low index of air (1)
-AR effect over a wide
wavelength range
Material
n
Si
3,45
TiO2
2,2
SiO2
1,5
ZnS
2,3
MgF2
1,4
Internal Quantum Efficiency and Total Reflectance of cell
- losses reduced to 3%
IQE0.3-4
100
100
90
90
1st layer: n1=2.2-2.6
2nd layer: n3=1.3-1.6
2
70
70
60
60
50
50
40
40
30
30
20
20
10
10
0
300
400
500
600
700
800
Wavelength (nm )
900
1000
1100
0
1200
Reflectance (%)
R min
2
IQE (%)
 n1 n3  n 2 n 0 
 2

2
 n1 n3  n 2 n 0 
2
80
80
ARC deposition methods
• vacuum Evaporation
•Sputtering
•Chemical Vapour Deposition
•Plasma Enhanced CVD
- thickness uniformity and reproducibility
-Stoichiometry control
Texturing
•pyramidal structures (about
10 microns) on wafer surface
• incident light is trapped
(multiple reflections)
-larger exposed area
-Oblique incidence (increased
collection efficiency at long l
Reflectance < 10%
with ARC < 4%
001
-wet anisotropic etch
NaOH or KOH based
111
010
100
-for Si <100> oriented,
structure is achieved by
intersection between the
<100> and <111> planes
(a=54.7°), allowing at
least two consecutive
reflections
-Different etch rates along
different crystallographic
directions:
etch rate about 35 faster for
<100> direction than for <111>
direction.
Texturing
-Inverted pyramids
structure reduces
reflection to few
percent
-honeycomb: traps
light in multicrystalline Si cells
Crystalline Silicon Cells
• High Efficiency cells: h 24.7%
• Industrially Scalable Cells
– New Design: h 20%
– Advanced Screen Printing: h 18-19%
• Industrial cells: h 14-15%
Thin polysilicon cells: h 10-14%
• Double AntiReflection Coating
(DARC) and inverted pyramids
• Passivating oxide on front (10
nm, Sf<10 cm/s)
• Selective emitter
• High purity material, high
resistivity FZ (>1 W*cm
=>Ld=1 mm)
• Passivating oxide on Back
(150-300 nm, Sb<10cm/s)
• Boron overdoping on back
contact regions
• 19.8% on multi-crystalline Si
PERL (Passivated Emitter and Rear
Locally diffused) Cell
Voc= 706 mV, Jsc=42.2 mA/cm2
FF=82,8%
h=24,7% (UNSW)
h 27.5% 100X
Back Sided Point Contact Solar
Cell
(Stanford University)
Point Contact cells
• Buried contact grid
(laser or mechanical),
Selective emitter,
Back Surface Field,
electroless metal
plating
EFF 19-20%
(>21% on bifacials)
UNSW
Buried Contact Solar Cell
BURIED
CONTACT
SOLAR CELLS
• Bi-facial cells: carriers are generated also by light incident on
the back side
EFF 21% (FhG-ISE) – 19% (Buried contacts)
•
“ emitter wrap-through” cells: back-contact solar cells,
with emitter contacts on the rear realized through laser –
drilled vias. 17% on 225 cm2 mc-Si cells (ECN)
• High efficiency solutions:
-Selective emitter obtained
by screen printing of a
doped paste
- Screen printed contact
buried cells
-Low temperature (SiN, aSi) layers deposition on
front and back for surface
and bulk passivation.
19.8% SiN ( GeorgiaTech)
Advanced Screen Printing
Future developments
-Short term: lower cost (thinner wafers, further efficiency
enhancement, new structures, etc)
-Long term: spectrum conversion to utilize the solar radiation
more completely
Crystalline silicon cells will dominate the market for a very long time
Thank you for your attention