Transcript Column-parallel CCD

LCFI Collaboration Status Report
Steve Worm
Rutherford Appleton Laboratory
for the Linear Collider Flavour
Identification (LCFI) Collaboration
Steve Worm – LCFI
DESY PRC - May 10, 2007
Outline
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LCFI activities
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Steve Worm – LCFI
Vertex software package
Column-parallel CCDs: CPC2
Clock drive and CPC-T test structures
Readout chip development
ISIS developments and results
Mechanical studies
DESY PRC - May 10, 2007
Vertex Package - Overview
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Goals
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Develop tools for the evaluation and optimisation of the vertex detector
Study benchmark processes; optimise the vertex detector
Package design overview
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Vertex package interfaces to MarlinReco framework
Framework consists of software processors, enabled and configured via XML
Input: LCIO events
Processors:
1. Track selection cuts for ZVTOP,
flavour tag, vertex charge
2. IP fit processor
3. ZVRES
4. ZVKIN
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Jet flavour MC truth information
Calculation of NN input variables
Training NN for flavour tag
NN outputs from trained nets
PlotProcessor for standard plots
Output: dedicated vertex class in LCIO format, with vertex information,
flavour tag inputs, NN flavour tag output and vertex charge
Big step towards full MC simulation and reconstruction (MOKKA+MarlinReco)
Steve Worm – LCFI
DESY PRC - May 10, 2007
Vertex Package - Comparisons
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Example plots: Purity vs. Efficiency
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Compares well with SLD/Fortran algorithm
Analysis at Z-peak energy with fast MC (left) and full Geant4 MC (right)
Excellent agreement with fast MC (identical inputs)
Very good agreement also with full MC (dependant on tracking input chosen)
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c (b-bkgr)
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Filled: LCFI (c++, MARLIN, fast MC)
Filled: LCFI (c++, MARLIN, MOKKA full MC)
Open: previous (Fortran, fast MC)
Open: previous (Fortran, Brahms full MC)
E. Devetak, M. Grimes, S. Hillert, B. Jeffery
Steve Worm – LCFI
DESY PRC - May 10, 2007
Vertex Package - Comparisons
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LCFI code
LCFI code
FORTRAN
FORTRAN
Joint probability and PT-corrected vertex mass
– Shown are the two most important flavour tag inputs
– Excellent agreement between LCFI code and Fortran result
– Details in recent LC Note
Steve Worm – LCFI
DESY PRC - May 10, 2007
Vertex Package - Verification and Status
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Verification Procedures and Results
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Stage 1: Comparisons between SGV and MARLIN using identical inputs
Stage 2: Same events passed through full MC simulation in MOKKA
Grid sample creation and MarlinReco debug in collab with MPI Munich, DESY
Compare MARLIN (MOKKA input), MARLIN (SGV input), and BRAHMS (TESLA TDR)
Profiling with Valgrind to check for memory leaks, improve performance
Preliminary results: MARLIN (c++) slightly outperforms SGV (Fortran)
Status
– Fully functional, ~20,000 lines of c++ code
– Released ~two weeks ago; available from the ILC software portal
– Considered a ‘highlight’ of the ILC Software Workshop (2-4 May)
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After release
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Tutorials for new users (starting soon)
Move to full tracking (currently use simplified tracking “cheaters”)
Move to more realistic vertex detector geometry (ladders, not cylinders)
Further optimisation of cuts, parameters and algorithms
Huge effort, and now available for use!
Steve Worm – LCFI
DESY PRC - May 10, 2007
ILC Vertex Detector Requirements
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Excellent point resolution
– Small pixels: ie 20 μm x 20 μm
– Close to the IP: inner radius ~1.5 cm
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Fast (low ocupancy) readout
– Column-parallel CCD: readout during 1 ms beam at 50 MHz (inner layer)
– In-situ Storage Image Sensor (ISIS): storage of data for readout in long
(~200 ms) inter-train gaps
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Extremely small material budget
– ~0.1% X0 per layer --> low power dissipation
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Overall detector geometry
– Sensor+layout concept actively being developed
– Pixels in 5 layers, ~109 channels
Steve Worm – LCFI
DESY PRC - May 10, 2007
Column-Parallel CCDs
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Fast Column-parallel CCDs (CPCCD)
– CCD technology proven at SLD, but
ILC sensors must be faster, more
rad-hard
– Readout in parallel addresses speed
concerns
– CPCCD’s feature small pixels, can be
thinned, large area, and are fast
– CPC1: two-phase, 400 (V) x 750 (H)
pixels, each 20  20 μm2
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“Classic CCD”
Readout time 
NM/Fout
Column Parallel
CCD
Readout time =
N/Fout
Bump-Bonded
CPCCD + Readout
CPCCD1
Steve Worm – LCFI
DESY PRC - May 10, 2007
Column-Parallel CCDs: CPC1 results and CPC2 design
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First-generation tests (CPC1):
– Noise ~100 e- (60 e- after filter).
– Minimum clock potential ~1.9 V.
– Max clock frequency above 25
MHz (design 1 MHz).
– Limitation caused by clock skew
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Next generation now available (CPC2):
– Busline free design (two-level metal)
– Large area ‘stitched’ sensor, choice of
epi layers for varying depletion depth
– Range of device sizes for test of
clock propagation (up to 50 MHz)
– Large chips are nearly the right size
Level 1 metal
Polyimide
Level 2 metal
Top &
Bottom
termination
Φ2 PIXELS
Φ1
OAT & test
field
Top &
Bottom
termination
Top &
Bottom
termination
Top &
Bottom
termination
OAT & test
Top &
field
Bottom
termination
PIXELS PIXELS
Top &
Bottom
termination
Top &
Bottom
termination
PIXELS
PIXELS
PIXELS PIXELS PIXELS PIXELS
Top &
Bottom
termination
CPC2-70
9.2 cm
Steve Worm – LCFI
2 x ISIS + top
termination
Top &
2 x ISIS + top
Bottom
termination
termination
PIXELS PIXELS PIXELS PIXELS
PIXELS PIXELS PIXELS PIXELS
PIXELS PIXELS PIXELS
2 x ISIS + top
termination
2 x ISIS + top
termination
2 x ISIS + top 2 x ISIS + top
termination termination
OAT & test
field
Active Devic
CPC2
DESY PRC - May 10, 2007
Wafer
2 x ISIS + top
termination
PIXELS
Top &
Bottom
termination
2 x ISIS + top
termination
Top &
Bottom
termination
To
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CPC2: Next generation CCD
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CPC2: second generation Column-parallel CCD
– Single-metal: (100 Ωcm @ 25 µm and 1.5 kΩcm @ 50 µm)
– 2 more wafers received with 2-level
metal (busline-free)
– Busline-free variant designed for
50 MHz operation
– Another 10 wafers in pipeline
ISIS test
structures
Busline-free design a big step!
CPC2-70
CPC2-40
Busline-free CPC2
Steve Worm – LCFI
CPC2-10
DESY PRC - May 10, 2007
Busline-Free CPC2 - First Results
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First test results from high-speed, double-metal CPC2-10
– Clear X-ray hits at up to 45 MHz despite significant clock feed-through
– Transformer drive (shown) is challenging due to numerous parasitics
55Fe
source removed
X-ray hits
CCD output (2-stage source follower), ~2 Vpk-pk clocks
Major result for LCFI (but that’s not all)…
Steve Worm – LCFI
DESY PRC - May 10, 2007
Busline-Free CPC2 - First Results
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Works at very low clock amplitude
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Clock amplitude for plot below is only 0.4 Vpk-pk
Significant noise induced from clock
Low clock due to very low dose inter-gate implant (not a resonance effect)
Further tests to use CMOS-based drive chip (CPD1)
Steve Worm – LCFI
DESY PRC - May 10, 2007
CPC2+CPR2 Hybrid Assemblies
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Tests on bump-bonded assemblies have started
– Two wafers-worth of bonded assemblies received
– First response to X-rays observed (below)
– Not all has gone smoothly…
T. Woolliscroft
ADC output
ADC output
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25
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55Fe
signal
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0
200 225 250 275 300 325 350 375 400 425 450 475 500 525 550 575 600 625 650 675 700
Time
Steve Worm – LCFI
DESY PRC - May 10, 2007
Capacitance Reduction Ideas for CCDs
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High capacitance CCD is challenging to drive
– 40 nF and ~2V clocks @ 50 MHz… >20 amps!
Working to reduce capacitance (and drive voltage)
– Inter-gate capacitance (Cig) is dominant; depends on gate and overlap sizes
– New sensor designs (open phase, pedestal gate, and shaped channel) can
reduce Cig by factor of ~4?
New test structure to test these designs - production starting at e2v
Cs
Cs
Phase1
Phase1
2Cig
Cig
2Cig
Phase2
Cs
Phase2
Cs
Steve Worm – LCFI
Open phase CCD
DESY PRC - May 10, 2007
Clock drive for CPC2
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Transformer-based driver
– Designed for 2 Vpeak-to-peak at 50
MHz and 40 nF (ie for CPC2-40)
– Planar air-core transformers on 10
layer PCB, 1 cm2
– Parasitic capacitance and inductance
of bond wires a major effect
– Works with “busline-free” CPC2
CPD1
Steve Worm – LCFI
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Transformers
CPD1 driver ASIC
– Designed for either large or small
sensors: 40 nF/phase at 50 MHz or
127 nF/phase at 25 MHz
– One chip drives both phases with
3.3V clock swing, 21 amps/phase
– 0.35m CMOS process, 3x8 mm2
DESY PRC - May 10, 2007
CPD1 Driver ASIC
CPD1 works well!
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Slew rate in slow mode
Rise time: 50ns, 2s, 4s
Features
– Three separate modes for operation over
a wide range of frequencies
– Bias circuitry, local decoupling
capacitance, control logic
– Designed to provide >2V peak-to-peak at
up to 50MHz
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Testing results
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Control circuitry works fine
Integrated capacitive load works well
Tested in package (inductance limited)
Full testing started in dedicated board;
internal (2 nF) and external (40 nF) loads
2nF load, Fast Mode, 25 MHz
PH1
PH2
PH1-Ph2
Steve Worm – LCFI
DESY PRC - May 10, 2007
Readout Electronics: CPR2 Readout Chip
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Designed to match the Column Parallel
CCD (CPC2)
– 20µm pitch, maximum rate of 50MHz
– 5-bit flash ADC, on-chip cluster finding
– Charge and voltage inputs
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Features for the CPR2 include
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Cluster Finding logic, Sparse read-out
Better uniformity and linearity
Reduced sensitivity to clock timing
Digital and analogue test I/O
Variety of test modes possible
9.5 mm x 6 mm die size, IBM 0.25µm
 Major piece needed for a full module
Steve Worm – LCFI
DESY PRC - May 10, 2007
CPR2a Readout ASIC
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CPR2 Readout ASIC: Works, but deadtime and some data loss for large clusters
CPR2a Readout ASIC:
– Pad-compatible, but with significant changes to digital
– Implemented features: Increased front-end memory depth, clustering now
4x6, compact layout, no repetition of time stamp, per-column threshold
– Next steps: Flag for corrupt or lost data, more digital outputs, optimisation of
analogue stages
Steve Worm – LCFI
DESY PRC - May 10, 2007
In-Situ Storage Image Sensor
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ISIS Sensor details:
– CCD-like charge storage cells in each pixel, CMOS or CCD technology
– p+ shielding implant (or epi) forms reflective barrier
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Operational Principles:
– Charge collected at photogate, transferred to storage pixel during bunch train
– 20 transfers per 1 ms bunch train
– Readout during 200 ms quiet period after bunch train
Reset transistor Source follower Row select transistor
photogate
transfer storage
pixel #1
gate
storage output sense
reset VDD
pixel #20 gate node (n+) gate
row
to column
select load
n+
buried channel (n)
p+ well
p+ shielding implant
reflected charge
Charge collection
High resistivity epitaxial layer (p)
Steve Worm – LCFI
substrate (p+)
reflected charge
DESY PRC - May 10, 2007
ISIS Properties and Status
5 μm
Global Photogate and Transfer gate
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ROW 3: CCD clocks
ROW 1: RSEL
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Global RG, RD, OD
RG RD
ISIS advantages:
– Low frequency clock -> easy to drive
– 20 kHz during capture, 1MHz readout
– ≈100 times more radiation hard (fewer
charge transfers)
– More robust to beam-induced RF
pickup
On-chip logic
ROW 2: CCD clocks
On-chip switches
ROW 1: CCD clocks
Process and Status:
– Combines CCD and active pixel
technologies
– Deep implant or custom epi needed
– Investigating CMOS and CCD vendors
Proof of principle device (ISIS1)
manufactured
OD RSEL
Column
transistor
Steve Worm – LCFI
DESY PRC - May 10, 2007
The ISIS1 Cell
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Array and Cell details
– 16x16 array of ISIS cells with 5-pixel buried
channel CCD storage register
– Cell pitch 40 µm x 160 µm
– No edge logic (pure CCD)
– Chip size 6.5 mm x 6.5 mm
Output and reset
transistors
OG RG
OD
RSEL
Column
transistor
OUT
Photogate aperture (8 μm square)
CCD (5x6.75 μm pixels)
Steve Worm – LCFI
DESY PRC - May 10, 2007
Radiation Damage Effects in CCDs
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Simulation of Charge Transfer
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-0.17eV trap
-0.44eV trap
Full 2D simulation in ISE-TCAD
Count signal e- trapped in pixel
CPU-intensive and time consuming
Simple analytical model gives
similar results
– Window of low charge transfer
inefficiency (CTI) between -40 °C
and 0 °C for 50 MHz
Very important for operation…
must confirm with data!
Steve Worm – LCFI
DESY PRC - May 10, 2007
Ladder Prototyping
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Ultra-low mass ladders a significant challenge
– 0.1% X0 per layer: active silicon sensor
thickness and not much else!
– Low power, low flow rate gas cooling only
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Foam structures being investigated
– Low mass, good rigidity
– Silicon+foam or Si+foam+Si sandwich
– Good thermal match for SiC and RVC
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Silicon Carbide (SiC)
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SiC as ladder support looks promising
Built 8% SiC on 25 μm Si  0.16 X0
0.1 X0 possible with ~5% foam
Ladder profiles with small T steps
look good (see plots at right)
Reticulated Vitreous Carbon (RVC)
– RVC ladder currently under test
– ~3% foam and 2x25μm Si  ~0.1 X0
– Sandwiched structure for rigidity
Steve Worm – LCFI
DESY PRC - May 10, 2007
Cooling Studies
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Goals
– Develop design capability- a predictive tool, not for layout optimisation
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Gas cooling test stand
– Major update with Perspex (insulating) ladders and end plates now complete
– Data collection underway with upgraded software
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Simulation of test stand
– Upgraded software, computing power
– New CFD model includes solid domain
– Still optimising inlets, heater elements
cooling
inlets
heater
elements
Steve Worm – LCFI
DESY PRC - May 10, 2007
Conclusions
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Physics Studies
– Vertex package released and available for public
– Important for ILC vertex-related physics studies
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Column-parallel CCD
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Second generation high speed CCD: CPC2 working at 45 MHz
Active programme of capacitance and clock amplitude reduction
Clock driver under development (CMOS and transformer)
Third-generation readout ASIC available, new one under design
In-situ Storage Image Sensor
– Proof of principle device works
– Design of small-pixel ISIS2 in progress
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Mechanical Studies
– Active programme of ladder mechanical prototyping
– Cooling test stand and simulation work converging
LCFI making excellent progress towards meeting the challenges of the ILC
Steve Worm – LCFI
DESY PRC - May 10, 2007