Transcript Low-Energy Design Methodologies for High

Design, Verification, and Test of
True Single-Phase Adiabatic Multiplier
Suhwan Kim
IBM Research Division
T. J. Watson Research Center, Yorktown Heights
Conrad H. Ziesler and Marios C. Papaefthymiou
Electrical Engineering and Computer Science
University of Michigan, Ann Arbor
Adiabatic Charging of an RC Tree
Charge and discharge load capacitance slowly to maintain small
voltage drop across MOS switches and recycle energy stored in load
capacitance.
Adiabatic Logic Families
Various adiabatic logic families,including 2N-2P, Pass-Transistor
Aiabdatic Logic (PAL), and Clocked CMOS Adiabatic Logic (CAL),
have been proposed.
True Single-Phase Energy-Recovery Logic (TSEL) is the first-ever
true single-phase adiabatic logic family. [Suhwan Kim and Marios.C.
Papaefthymiou, ISLPED’98].
Source-Coupled Adiabatic Logic (SCAL) is an enhancement of TSEL
with improved scalability and energy efficiency across a broad range
of operating frequencies. [Suhwan Kim and Marios. C.
Papaefthymiou, ISLPED’99].
SCAL-D: Source-Coupled Adiabatic Logic with
Diode-Connected Transistors
Basic characteristics of SCAL-D are the same as with SCAL/TSEL.
single-phase AC power-clock operation
simple AC power-clock generator
simple to cascade
Individually tunable current source attached to each gate.
broad range of operating frequencies with minimum-size transistors
Diode-connected transistors used to improve performance.
PMOS Logic Structure in SCAL-D
Each logic gate comprises a pair of cross-coupled transistors, diodeconnected transistors, current control switches, a pull-up evaluation
tree, and a tunable current source.
Operation of PMOS Logic in SCAL-D
NMOS Logic Structure in SCAL-D
Basic structure is the same as in PMOS SCAL-D, with NMOS
devices replaced by PMOS devices
Cascading of SCAL-D Logic
Energy consumption is minimized by individually setting the W/L ratio
of each current source and globally setting the biasing voltages equal
to the minimum possible value. This value depends on the gate’s
output load and speed requirement.
Voltages of Output Nodes in
Cascaded SCAL-D
8-bit Multiplier and BIST Logic in SCAL-D
Schematic Diagram of
Full-Adder Multiplier Cell in SCAL-D
Full-Custom Layout of
Full-Adder Multiplier Cell in SCAL-D
buffer
1-bit full adder
and
buffer
Full-Custom Layout of
8-bit Multiplier and BIST Logic in SCAL-D
BILBO 1
self-test
controller
8-bit
multiplier
BILBO 2
Transistor Count and Area of
8-bit Multiplier and BIST Logic in SCAL-D
Transistor Count
Area
11,854
0.710mm^2
Built-in self-test logic
8-bit multiplier
Evaluation with Voltage Scaling
In HSPICE simulations, our SCAL-D 8-bit multiplier and BIST logic
outperformed corresponding static CMOS designs that were
operating with supply voltages scaled for minimum energy
dissipation.
Design Verification of
8-bit Multiplier and BIST Logic in SCAL-D
power-clock
BILBO control
signals s1,s2
output sequence ix
of BILBO 1
output sequence ox
of BILBO 2
The results of HSPICE simulation were compared directly against the
corresponding results of Verilog-HDL simulation using CAD tools we
developed.
Floor-plan of Test-Chip
Two identical multipliers with associated BIST logic, an internal
power-clock generator, adiabatic-to-digital converters, and pads were
included.
Die Photograph of Test-Chip
Fully custom design
0.5um n-well CMOS process
DIP40 package
4.83mm^2
130 MHz operation with 3.0V
Experimental Setup
digital
oscilloscope
(TDS754D)
test-board
signal generator
(HP8647A)
digital
multi-meters
DC
power supply
Test-Board
test-chip
variable resistors
to control PMOS and NMOS
biasing voltages
connector for
external power-clock
switches for
input signals
Functional Test in Self-Test Mode:
50MHz/3.0V
power-clock
BILBO control
signals s2
output sequence ix
of BILBO 1
output sequence ox
of BILBO 2
Functional Test in Self-Test Mode:
130MHz/3.0V
power-clock
BILBO control
signals s2
output sequence ix
of BILBO 1
output sequence ox
of BILBO 2
Energy Measurement Procedures
chip
power supply
 ( IVDD Vdd / 2  ( IVDD  IPC) Vdd / 2 


N T   (vPC  iPC)

Ecycle   
 dt N
0
 (VBP  IBP)


  (VBN  IBN)



Measured Energy Consumption of
8-bit Multiplier and BIST Logic in SCAL-D
Energy consumption in the 8-bit multiplier and BIST logic,
implemented entirely using SCAL-D, for various PMOS and NMOS
biasing voltages at the operating frequency range of 40-130 MHz.
Relative Difference of Energy Consumption
Between TDS754D and HSPICE
Measured energy consumption of SCAL-D circuits correlates well
with HSPICE simulation results for the same operating frequencies,
amplitude of AC power-clock, DC supply voltage, and PMOS and
NMOS biasing voltages.
Measured Waveforms of Test-Chip
Operated in BIST Mode - 130MHz/3.0V
power-clock
BILBO control
signals s2
output sequence ix
of BILBO 1
output sequence ox
of BILBO 2
Summary
True single-phase source-coupled adiabatic logic family
Lower energy dissipation than static CMOS across broad range of
operating frequencies.
To demonstrate practicality of our single-phase adiabatic logic, we
designed an 8-bit adiabatic multiplier in 0.5um standard CMOS
process.
The 8-bit adiabatic multiplier and BIST logic was verified, fabricated,
tested, and measured up to 130 MHz.