Transcript Design for Printability

Design for Printability
From Device to Circuit
for
Flexible Electronics
Tsung-Ching (Jim) Huang
Tim Cheng
February 10th 2007
Outline

Introduction


Motivation – Why design with flexible electronics
Limitation – What difference from Si MOFET circuit design
 A-Si:H
TFT
 Organic TFT

Robust Circuit Design for Flexible Electronics

A-Si:H TFT
 Robust

building blocks
Organic TFT
 Cell
library design
 Printable circuit layout
2
Why Design with
Flexible Electronics
Cost
S
ET
F
O
iM
TFT
U. Tokyo
ASU
Performance
Plastic Logic
Poly IC
Polymer Vision
3
What Differences from
Si MOFET Circuit Design
Si MOFET
A-Si:H TFT
Organic TFT
Process
Temperature
1000 °C
200 °C
< 100 °C
Process
Technology
Photolithography
multi-layers w/via
Photolithography
Multi-layer w/via
Roll-to-Roll &
Ink-Jet w/o via
Design Rule
<= 90 nm
20 μm
50 μm
Substrate
Wafer
Glass/Plastic
Plastic/Metal Foil
Device Type
N-type & P-type
N-type
P-type
Mobility
1500 cm2/Vs
1 cm2/Vs
0.5 cm2/Vs
Cost/Area
High
Medium
Low
Lifetime
Years
Months
Days
4
Outline

Introduction


Motivation – Why design with flexible electronics
Limitation – What difference from Si MOFET circuit design
 A-Si:H
TFT
 Organic TFT

Robust Circuit Design for Flexible Electronics

A-Si:H TFT
 Robust

building blocks
Organic TFT
 Cell
library design
 Printable circuit layout
5
Pseudo-Complementary
A-Si:H TFT Inverter
VGG
VDD
VDD
M3
M1
M1
OUT
M2
OUT
IN
M4
IN
VSS
Pseudo-Complementary
TFT Inverter
M2
VSS
N-TFT
Inverter
6
A-Si:H TFT
Inverter Transfer Function
Inverter Transfer Function
C-TFT Inverter
18
Output voltage (volt)
N-TFT Inverter
13
8
3
-2 -2
3
8
18
13
Input voltage (volt)
Model
VDD
VGG
VSS
N-TFT
RPI (W50L5)
18 V
--
-2 V
C-TFT
RPI (W50L5)
18 V
21 V
-2 V
7
Output Reponses of
N-TFT Inverter Chain
• Signal strength after propagation will
diminish due to insufficient noise margin
• Insufficient for circuit design with a
certain degree of complexity
8
Output Reponses of
C-TFT Inverter Chain
• Signal strength after propagation
remains at the same level as input signal
• Sufficient for circuit design of higher
complexity
9
Immunity to
Threshold Voltage Variation
VTH
VTH’
VGG VDD
VSS
1.1 V
5.5 V
21 V
-2 V
18 V
10
Compensation to
Threshold Voltage Variation
VGG
VDD
VDD
M3
M1
M1
OUT
M2
OUT
IN
M4
IN
M2
VSS
VSS
Pseudo-Complementary
TFT Inverter
N-TFT
Inverter
VTH
VTH’
VGG VDD
VSS
1.1 V
5.5 V
29 V
-2 V
18 V
11
Outline

Introduction


Motivation – Why design with flexible electronics
Limitation – What difference from Si MOFET circuit design
 A-Si:H
TFT
 Organic TFT

Robust Circuit Design for Flexible Electronics

A-Si:H TFT
 Robust

building blocks
Organic TFT
 Cell
library design
 Printable circuit layout
12
Published OTFT Model
Vg
Vs
~ pF
~ pF
Cgs
Cgd
Rs
Rd
~ kΩ
Vd
~ kΩ
Id
Top Gate
G
Dielectric
Semiconductor
S
D
Substrate L
S
Bottom
Contact
Ref: M. Fadlallah et al, Plastic Logic, J.
Applied Physics 2006
13
Printed Passive Component
Physical dimension for
high-impedance
resistance:
1KΩ  2mm x 1mm
• Ink-jetted resistance normally can have much
higher value than standard clean-room process
• High impedance resistance can be beneficial
in implementing pseudo-complementary design
(190ºC, 1-layer)
Resistance
50 μm drop size
Capacitance
Ref: D. Radinger et al, J. Electron Device ‘04 14
Pseudo-Complementary
OTFT Inverter
VDD
Ratio-less Logic
OTFT Inverter Transfer Function
3.5
IN
Vsub@VDD
R
OUT
Output Voltage (volt)
3
Vsub@VSS
2.5
2
1.5
1
0.5
0
VGG VSS
• PMOS together with
necessary series
resistance is used for
OTFT equivalent model
0
0.5
1
1.5
2
2.5
3
3.5
Input Voltage (volt)
Model
VDD
VSS
VGG
R
AMI 0.6 μm
3.3 V
0V
-1 V
1 kΩ
15
Inverter Layout
VDD
32 Units
G
S
D
IN
D
S
G
D
G
S
G
D
G
S
G
OUT
G
D
S
R
46 Units
VGG
VSS
1 Unit = 50 μm
16
Output Response to
Threshold Voltage Variation
• PC-OTFT
exhibits robustness
again VTH variation
due to electrical or
chemical
degradation
17
Output Response of
Inverter Chain
• Signal propagation
will not diminish in
PC-OTFT inverter
design because of
ratio-less design
• After 10-stage
signal propagation,
ordinary OTFT
inverter can not
generate the same
signal strength
18
2-Input NAND Layout
VDD
IN_X
S
R
D
S
D
S
D
S
D
S
D
S
D
D
S
D
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
OUT
S
VSS
D
S
D
S
D
S
D
S
D
S
D
D
S
D
IN_Y
VDD
2-INPUT
NAND
S
D
G
S
G
D
G
S
G
D
G
S
D
G
S
G
D
G
S
G
D
G
S
D
G
S
G
D
G
S
G
D
G
GND
79 Units
85 Units
19
3-Input NAND Layout
VDD
IN_A
OUT
S
D S D S D
G G G G G
S D S D S D
G G G G G
D S D
G G
S D S D S D
G G G G G
S D S D S D
G G G G G
S
G G G G G
D S D S D
G G G G G
S D S D S D
G G
D S D
G G G G G
S D S D S D
G G G G G
S D S D S D
S
D S D S D
G G G G G
S D S D S D
G G G G G
D S D
G G
S
S D S D S D
G G G G G
IN_B
D S D S D
G G G G G
GND
R
IN_C
VSS
90 Units
3-INPUT NAND
115 Units
20
2-Input NOR Layout
VDD
IN_X
S
D
G
S
G
D
G
S
G
D
S
G
D
G
S
G
D
G
S
G
D
D
G
S
G
D
G
IN_Y
S
D
G
S
G
D
G
S
G
D
S
G
D
G
S
G
D
G
S
G
D
D
G
S
G
D
G
OUT
R
S
D
G
79 Units
VSS
S
G
D
G
S
G
D
G
2-Input NOR
S
D
G
S
G
D
G
S
G
GND
D
G
61 Units
21
PC-OTFT
D Flip-Flop Output Response
• D-FF composed
of PC-OTFT
NAND gates
exhibits good
noise-margin in
output response
22
2-Bit ROM Layout
VDD
• Ex1.
GND
D S D
G G
Input [ 0 1 0 0 ]
D S D
G G
D S D
G G
S D
G
S D
G
S D
G
S D
G
S D
G
S D
G
S D
G
S D
G
Output [ 0 1 0 1]
D S D
G G
WL[0]
• Ex2.
79 Units
WL[1]
S D
G
S D
G
S D
G
S D
G
Input [0 0 1 0]
WL[2]
BL[2]
BL[1]
GND
R
GND
R
R
R
BL[0]
S D
G
S D
G
S D
G
WL[3]
S D
G
Output [0 0 1 0]
GND
2-Bit ROM
BL[3]
GND
89 Units
23
Summary





Flexible electronics technology is now emerging and more
commercial applications will become available
Low-cost, bendable, thin-film, and light-weight properties are
highly desirable in consumer electronics
Circuit reliability and lifetime remain to be the biggest challenges
to make wide use and market penetration
Novel circuit building blocks and printable layout are
demonstrated to extend circuit lifetime
Significant innovations in material/device/design/testing area
are still required
24
Q&A
Thank you for your attention !!
25