Transcript Temperature-Aware Design

Temperature-Aware Design
Presented by Mehul Shah
4/29/04
The Problem
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Power & Thermal densities are increasing
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Operating Vdd scaling much more slowly (ITRS)
Cost of cooling rising exponentially
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Currently @ 50W/cm2, 100W/cm2 @ 50nm technology
Power density doubles every 3 years
$1 - $3 per Watt of power dissipation
Packages designed for worst case power
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Hot spots – heat dissipation non-uniform across chip
Low-Power design techniques not sufficient
Big Hammer : Global Clock Gating limits performance
Impact of Temperature on Design
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Increased Delay, Lower Reliability
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Slower Transistors
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Higher Leakage Power
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By orders of magnitude at higher temperature
Leakage becoming more significant than switching power
Higher Metal Resistivity
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Carrier mobility lower at higher
temperature
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Inverter 35% slower at 110 C vs. 60 C
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Lower Mean-Time-To-Failure (MTF)
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Copper 39% more resistive at 120 C vs. 20 C
MTF = MTFo exp (Ea / kb T)
MTF decreases exponentially w/ Temperature
Moral of the Story
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Problem: Temperature adversely affects power, performance &
reliability
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Solution: “Temperature-Aware” Design
Temperature Aware Design
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Thermal Modeling
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Estimate Operating Temperature
Simple : Allow architects to easily reason about
thermal effects
Detailed : Model runtime temperature at
Functional-Unit granularity
Computationally Efficient
Flexible : Easily extend to novel architectures
Dynamic Thermal Management
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Use runtime behavior and thermal status to
adjust/distribute workload among Functional-Units
Talk Outline
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Thermal Modeling
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Model Description
Validation & Case Studies
Dynamic Thermal Management
Results
Conclusions
References
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Kevin Skadron et. al, “Temperature-Aware
Microarchitecture”
Wei Huang et. al, Compact Thermal Modeling for
Temperature-Aware Design”
Thermal Modeling
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Thermal model
interacts with Power,
Performance,
Reliability models
Design convergence
requires several
iterations
Heat Flow vs. Electrical Phenomenon
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Both can be described by the same
differential equations
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Describe design as a Thermal RC circuit
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Heat Flow = Electrical Current
Temperature = Voltage
Capacitance = Heat Absorption Capacity
Node = Functional Block
Solve RC equations to obtain Node
Temperature
HotSpot Package
Equivalent Model
Equivalent Model (Continued)
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Die Area divided into micro-architectural blocks
Spreader, Sink divided into five blocks
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Rsp, Rhs areas under the die
Trapezoids not covered by the die
Rconvective represents thermal resistance from package to air
RC Model
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Vertical R’s : heat flow between layers
Lateral R’s : heat diffusion within a layer
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R=t/k*A
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R1 = Block1 to Spreader, R2 = Block1 to rest of the chip
t : thickness
k : thermal conductivity of the material
A : Cross-sectional area
C=c*t*A
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c : thermal capacitance per unit volume
Require empirical scaling factor due to lumped model
HotSpot Validation
Fallacy of Using a Power Metric
Compact Thermal Model
Equivalent Model
Equivalent Model (Cont.)
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Compact Model vs. HotSpot
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Arbitrary granularity grid
Thermal interface material
Spreader, Interface under the die are divided into chip
granularity
Primary Heat Flow Path
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Rvertical = t / (k * A)
C = Alpha * cp * ρ * A
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Alpha : To account for lumped capacitor model
Cp : specific heat
ρ : material density
Equivalent Model (Secondary Path)
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Interconnect Thermal
Model
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Self-heating power &
wire length prediction
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Pself = I2R
R = ρ m * L / Am
Equivalent Model (Secondary Path, Cont.)
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Equivalent Thermal Resistance
Model Validation & Evaluation (Primary)
Transient
Steady State
Model Validation (Secondary)
Case Study
Thermal Management
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Dynamic Thermal Management
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Emergency Threshold temperature above
which chip is in thermal violation
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Trigger Threshold temperature above
which DTM is applied
DTM Techniques
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Temperature-Tracking Frequency Scaling
Feedback controlled Fetch Toggling
Migrating Computation
Dynamic Voltage Scaling (DVS)
Global Clock Gating
DTM Results
Conclusions
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Accurate Thermal models are essential for early
design estimation
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Models are similar to electrical RC networks
Arbitrary granularity for localized temperature information
Model all parts of the package
Architectural Techniques can reduce demands on the
IC package by
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Dynamically adjusting workload to avoid emergencies
Reducing Hot Spots