Transcript Document

SOI, 3D and Laser Annealing
for ILC
S.Cihangir-Fermilab
Representing Contributors from:
Fermilab, Bergamo, Cornell, Purdue
More details-Talks by:
Ron Lipton at SiD Workshop at Fermilab and Oxford
Ray Yarema at CERN Atlas-CMS Electronics Workshop
Selcuk Cihangir, Fermilab
LCWS 2007, DESY
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Outline
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SOI (Silicon-on-Insulator) devices
3D and SOI Driving Technologies
SOI Activities at Fermilab:
– OKI process
– American Semiconductor FLEXFET process
3D Activities at Fermilab:
– VIP1 chip for ILC
Other Activities at Fermilab:
– Thinned, edgeless sensors
– Laser annealing
– Simulation
Selcuk Cihangir, Fermilab
LCWS 2007, DESY
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Silicon-On-Insulator
Buried oxide (200nm)
Bulk CMOS
SOI CMOS
Isolation from the bulk silicon:
Suppression of bottom junction 
Lower parasitic capacitance and therefore faster switching and
lower power consumption…
Enabling operation at higher temps (250oC)
Lower SEU rate.
Denser layout (100% diode fill factor)
Selcuk Cihangir, Fermilab
LCWS 2007, DESY
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SOI (Cont)
Industry accepted overall improvement:
25% faster
50% lower power consumption
10% smaller die size
Applications:
High Speer ProcessorsIBM and Motorola: Power PC
AMD Athlon-64
Graphic ProcessorSony/IBM/Toshiba: PlayStation 3
High-speed Serial Data CommuniationMitsubishi: 10 GBps SERDES
Ultra Low Power SoC (System on a Chip)OKI Solar cell watch
Satellite systems, spacecraft electronics
Selcuk Cihangir, Fermilab
LCWS 2007, DESY
And HEP…..
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SOI (Cont)
Common method of SOI production:
(Soitech illustration)
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SOI is formed by bonding a thin
active circuit layer on a substrate
(handle wafer) that has an oxide
layer (~200 nm) on the surface.
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The handle wafer can be high quality,
detector grade silicon, which opens
the possibility of integration of
electronics and fully depleted
detectors in a single wafer with very
fine pitch and little additional
processing.
Active
BOX
Substrate
(detector material)
Steps for SOI wafer formation
Selcuk Cihangir, Fermilab
LCWS 2007, DESY
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New Detector Technologies
This gives ways to new technologies which are applicable to HEP
detectors, ILC in particular:
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SOI - handle wafer engineering: Wafer
thinning, bonding and alignment
Edgeless sensors
Three dimensional (vertical) integration of
electronics and sensors
– Reduce R, L, C for higher speed
– Reduce chip I/O pads
– Provide increased functionality
– Reduce interconnect power and
crosstalk
Through wafer via formation and
metallization
Optical In
Power In
Digital Layer
Analog Layer
50 um
Sensor Layer
Physicist’s Dream
3D Integration
SEM of 3 vias
using Bosch
process
Selcuk Cihangir, Fermilab
Opto Electronics
and/or Voltage Regulation
Optical Out
Via using
oxide etch
process
(Lincoln
Labs)
LCWS 2007, DESY
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Group Initiatives
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Sensors: Thinned, edgeless
Chip fabricated in OKI 0.15 m SOI process
– Includes sensor and one layer of electronics for electron microscope
Chip being designed in American Semiconductor 0.18 m SOI process
(SBIR)
– With pixel sensor layer and one or more electronics layers for ILC
vertex detector
3D chip (VIP1) being fabricated in MIT LL 0.18 m SOI multi-project run.
– 3 tier demonstrator chip for ILC vertex detector
Bonding Technologies (being explored)
– Cu-Sn bonding of FPIX chips/sensors
– DBI bonding of 3D chips to MIT sensors
Laser annealing (Cornell)
Simulations
Selcuk Cihangir, Fermilab
LCWS 2007, DESY
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Sensor Studies
We are producing a set of thinned, “edgeless” sensors at
MIT-LL as a initial test of these concepts
• Produce a set of detectors thinned to 50-100 m for beam and
probe tests.
– Validate process
– Understand performance
– Measure the actual dead region in a test beam
• Masks designed at FNAL
– Test structures
– Strip detectors (12.5 cm and ~2 cm)
– FPiX2 pixel detectors (beam tests)
– Detectors to mate to 3D chip
• Wafers due in September
Selcuk Cihangir, Fermilab
LCWS 2007, DESY
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MIT-LL Wafer designed at FNAL
3D test detectors
Strip detectors
Test structures
Fpix2 pixel
detectors
Due ~September
Strip detectors
Selcuk Cihangir, Fermilab
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SOI Concept for HEP
Advantages:
Low capacitance, no
parasitic charge
Rad hard (> 1MRad)
Low Power, low noise
100% diode fill factor
Minimal interconnects,
low node capacitance
High resistivity silicon
wafer, thinned to 50100 microns, full
depletion, large signal
Backside implanted after thinning,
before front side wafer processing,
laser annealed after processing
Active edge
processing
Fermilab Involvement:
1. OKI 0.15 micron SOI process
2. American Semiconductor 0.18 m SOI process (Flexfet)
Selcuk Cihangir, Fermilab
LCWS 2007, DESY
Signal diappears at Vb~16V10
Fermilab Involvement
1. OKI 0.15 m SOI process (Mambo SOI X-Ray Chip)
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Fermilab has submitted a design to a
KEK sponsored multi project run at
OKI which incorporates diode
formation by implantation through
the BOX. The chip incorporates a
64 x 64 26 micron pitch 12 bit
counter array for a high dynamic
range x-ray or electron microscope
imaging.
Max 13 m implant pitch is
determined by the “back gate”
effect where the topside transistors
thresholds are shifted by handle
potential
Just received!
To be tested at Laser Test Stand.
Image by SEM.
Selcuk Cihangir, Fermilab
Counting pixel detector plus readout circuit
• Maximum counting rate ~ 1 MHz.
• Reconfigurable counter/shift register
• 12 bit dynamic range
• Limited peripheral circuitry
• Drivers and bias generator
• Array size 64x64 pixels
• 350 micron detector thickness
LCWS 2007, DESY
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Fermilab Involvement
2. American Semiconductor 0.18 m SOI process (Flexfet)
from Y. Arai (KEK)
In
Out
Bottom gate shields
the transistor channel
from charge buildup in
the BOX caused by
radiation, as well as
from the voltage on the
substrate and removes
the Back Gate Voltage
problem.
N+ P
N+
BOX
P+ N
P+
Back gate
Silicon Substrate
Optimization is on-going, to be
tested. Also, possibility of a
pinning layer to shield the analog
pixel from digital activity.
Signal diappears at Vb~16V
Substrate voltage acts as a back gate bias and changes
the transistor threshold - like another gate.
Requires minimum ~15 micron diode spacing to control
surface potential.
Fermilab designed for ASI a demonstration SOI Pixel cell with voltage ramp
for time marker, sampling for crossing time, analog pulse height and counter
for timestamp. All simulated.
Selcuk Cihangir, Fermilab
LCWS 2007, DESY
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VIP1 Chip
3D chip at MIT LL 0.18 m SOI multi-project run
Vias
Goal - demonstrate ability to implement a
complex pixel design with all required ILC
properties in a 20 micron square pixel.
Previous technologies limited to very
simple circuitry or large pixels.
Three levels (tiers) of transistors, 11
levels of metal in a total vertical height of
only 22 m.
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Key features: Analog pulse height, sparse
readout, high resolution time stamps.
Time stamping and sparse readout occur in
the pixel. Hit address found on array
perimeter.
64 x 64 pixel demonstrator version of
1K x 1K array.
Edgeless sensor to be bonded later.
Selcuk Cihangir, Fermilab
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VIP1 Chip (Cont)
Pad to sensor
Tier 3
Sample 1
Analog
Sample
1
Sample
2
Delay
Vth
S. Trig
To analog output buses
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Tier 2
Digital time stamp bus
Write data
Time
Stamp
b0 b1
Analog T.S.
b2 b3 b4
Read data
Analog ramp bus
Analog time output bus
Data
sparsification
In
Inject
Test input S.R.
pulse
Out
Y address
X address
Selcuk Cihangir, Fermilab
D FF
Data clk
Front end power ~ 1875 W/mm2 (before cycling)
175 transistors in 20 µm pixel.
Due in August.
Tier 1
Token In
Pixel
skip
logic
Q
Token out
S
R
Read
all
Read data
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Laser Annealing
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After thinning a backside contact must be
formed. This is usually done by implantation
and high temperature furnace annealing which will destroy the front side CMOS
SOI circuitry. An alternative is laser
annealing of the backside implantation,
which limits the frontside temperature to
less than 500o C.
Use a raster scanned eximer laser to melt
the silicon locally – this activates the
implant and repairs the implantation damage
by re-crystallizing the silicon.
Diffusion time of phosphorus in molten
silicon is much less than cooling time
therefore we expect ~uniform distribution
in melt region.
0.80
XeCl
Ruby
Yag
Linear (XeCl)
0.70
Melt Depth(um)
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0.60
0.50
y = 0.3849x - 0.4029
0.40
0.30
0.20
0.10
0.00
0
0.5
1
1.5
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2.5
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3.5
Laser Energy (J/cm^2)
Oak Ridge studies of melt depth vs laser energy
To study and qualify this process we took a sample of Run2b HPK, low leakage 4x10 cm2, strip
detectors and reprocessed them: backgrind by ~50 microns to remove back implant and
aluminization, polish, re-implant detector using 10 KeV phosphorus at 0.5 and 1.0x1015/cm2, laser
anneal and measure CV and IV characteristics.
AMBP - 0.8, 1.0, 1.2 J/cm2, 248 nm laser
Cornell - 1.0 J/cm2 305 nm laser
Selcuk Cihangir, Fermilab
LCWS 2007, DESY
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Laser Annealing Results
(Cornell-Fermilab)
Ileak (microAmps)
Preliminary
Vbias (Volts)
Selcuk Cihangir, Fermilab
LCWS 2007, DESY
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SIMS Measurements
Secondary Ion Mass Spectroscopy
provides implant depth profiles by
analysis of ions ejected from the
surface upon ion bombardment.
Two samples, before and after
1.2 J/cm2 248 nm laser anneal:
Goal was >2x1019 concentration
Melt depth ~300 nm.
Laser melt depth is close to
expectation, phosphorus
concentration close to
expectation.
Additional sintering at 400oC
and “forming gas” treatment
should improve leakage.
Plan to explore leakage current
as a function of implantation
dose, laser energy and sensor
thickness.
Selcuk Cihangir, Fermilab
LCWS 2007, DESY
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More to do!
In addition to what were mentioned above:
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Can we retain good, low leakage current, detector performance through
the CMOS topside processing?
How does the charge in the BOX due to radiation and potential of the
handle wafer affect the operation of the top circuitry?
How does topside digital circuitry affect the pixel amplifier?
Simulations: 3D device simulation tools (Silvaco) - extremely useful to
understand charge collection, back gate, and digital/analog coupling
effects.
Selcuk Cihangir, Fermilab
LCWS 2007, DESY
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Final Words!
(For now)
Vertically integrated (3D) electronics are
becoming available.
• Much of this technology is ideally suited
to HEP vertex detectors.
• Fermilab is exploring
– Monolithic 3D Circuitry
– SOI sensors
– Wafer bonding technologies
With focus on ILC, but also looking at
applications in LHC, x-ray imaging, …
• The technology has promise for X-ray
detectors, electron microscope focal
planes, imaging, and astronomy.
More to come and to say in the near future….
Selcuk Cihangir, Fermilab
LCWS 2007, DESY
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Extras
Selcuk Cihangir, Fermilab
LCWS 2007, DESY
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Fermilab SOI Detector Activities
SOI detector development is being pursued by Fermilab at two different foundries:
OKI in Japan, and American Semiconductor Inc. (ASI) in US .
The two processes have different characteristics as seen below.
Process
SOI wafer
Backside
0.15m Fully-Depleted SOI CMOS
process,
1 Poly, 5 Metal layers (OKI Electric
Industry Co. Ltd.).
Process
Dual gate transistor (Flexfet),
Wafer Diameter: 150 mm,
Top Si : Cz, ~18 -cm, p-type, ~40 nm
thick
Buried Oxide: 200 nm thick
Handle wafer: Cz、>1k -cm (No
type assignment), 650 m thick
(SOITEC)
No poly, 5 metal
(American Semicondutor /
Cypress Semiconductor.)
SOI
wafer
Wafer Diameter: 200 mm,
Handle wafer: FZ>1k -cm (n
type)
Backside
Thinned to 50-100 m,
polished, laser annealed and
plated with Al.
Thinned to 350 m, no contact
processing, plated with Al (200 nm).
OKI Process
Selcuk Cihangir, Fermilab
0.18m partially-Depleted dual
gate SOI CMOS process,
LCWS 2007, DESY
ASI Process
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