Transcript ITRS Roadmap Design Process Open Discussion EDP 2001

ITRS Roadmap
Design Process
Open Discussion
EDP 2001
Donald Cottrell
Si2, Inc.
July 18, 201505/03/2000
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EDP '2001
Technology Trend - The Big
Transistors
1200
Transistors per Chip
1000
Millions
800
600
400
200
0
180
165
150
130
120
110
100
Designer Productivity
Feature Size
Transistors/Chip
Transistors per Month
Transistors/cm
Year
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Technology Trend - The Bad
%
% Mixed Signal
1999
2000
2001
Memory
2002
Cores
2003
2004
2005
New Design
Year
Diversity
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Technology Trend - The Ugly
 Mutual Coupling
 Coupled
 External
 Power
 di/dt
 IR Drops
 Electromigration
Capacit ance (pF/Lengt h)
 Noise
Total Cap
Self Cap
Mutual Cap
 High Frequency
 Transmission lines
 Reflections
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D ecr easing Feat ur e Size
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Breaking Down the “Walls”
Digital
Analog
Software
Architecture
RTL
Synthesis
FloorPlan
Layout
Checking
Mask Prep
Manufacture
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Breaking Down the “Walls”
Magma’s single unified data model enables
a correct-by-construction design flow.
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EDA Evolution - 2001
1
2
ASCII
ASCII
ASCII
ASCII
MW
Genesis
3
ASCII
ASCII
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Reality
 No external vendor meets all IC design needs,
All EDA vendors together don’t meet all needs.
 Nearly impossible for startups to break into the business due
to integration barriers,
Startups enter business with intent to be
purchased,
BUT once purchased by “big guys”, a time
lag and loss of innovation result.
 Industry partnerships provide value,
BUT integration acts as a barrier.
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All or Nothing at All
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The Need - Customer Choice
CorelDraw
Access
Lotus123
FrameMaker
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Customize Solution to Fit the Need
Calibre
SE
Mars-XTalk
Fire&Ice
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A Better Model
1
2
4
ASCII
Open
Model and
API
ASCII
ASCII
ASCII
MW
Genesis
3
ASCII
ASCII
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EDA System Needs
Architectural
• High Performance integration and tools: Architectural
Design
Design
Architecture and Assembly
Function, Performance, Power, ..
RTL through Mask design and analysis
RTL
RTL
Design
Design
• Constraint driven design tools
(power, timing, signal integrity, …)
Delay
Extraction
• Common Calculation Engines
Final
Final
Verification
Verification
• Abstracted Model Builders
Industry Standard interfaces
Test
Generation
Industry Standard
Design API
• Concurrent design and analysis
Incremental
Incremental
Extraction
Extraction
Delay
Power
Function
Properties
Process Lib
Floor Plan
Plan
Floor
Place&Route
Place&Route
Cell and
Core Library
Cell Geometry
Abstract
Detailed
Synthesis
Synthesis
• Integration via Open Architecture
Industry-standard data model
Industry-standard API
• Incremental analysis and optimization
Calculation
Engines
Substrate
Dielectric
Metal
Via
Signoff
Signoff
Database
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Standards vs. Innovation
 Did SQL hurt Relational Database sales?
 Did MAC grow faster than PC?
 Are we happy with the rate of university research
technology transfer?
 Is there a better way to do cooperative design? SoC?
 Can we continue with ASCII file exchange vs. true
interoperability?
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Discussion
 Do we really need an Open Infrastructure?
 Does one-size fit all?





P
ASIC
Return
Complexity
 Will an EDA MicroSoft emerge - Is that bad?
 Can an EDA Linux model work?
Analog/RF/MEMS
COTS
ASIC (compiled HDL --> gates)
High-volume custom (uP, DSP, embedded memory, reprogrammable)
SOC (high integration, low cost, low TTM)
Memory
 Are product markets significant?
 Portable & Wireless, Broadband, Internet Switching,
Mass Storage, Consumer, Computer, Automotive
 Can we develop the necessary metrics?
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Market Drivers
Market Drivers
I. Portable & Wireless
1. Size/weight: peak in 2002
2. Battery life: peak in 2002
3. Function: 2X every 2 years
4. Time-to-Market: ASAP
5. Time-in-Market: decreasing
II. Broadband
1. Bandwidth: 2X every 9 months
2. Function: 20%/year increase
3. Deployment/Operational Cost: flat
4. Reliability: asymptotic to 99.999%
target
5. Time-in-Market: long
III. Internet Switching
1. Bandwidth: 4X every 3-4 years.
2. Reliability
3. Time-to-Market: ASAP
IV. Mass Storage
1. Density: 60% increase per year
2. Speed: 2X by 2005
3. Form factor: Shift towards 2.5"
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ASIC
Analog
Custom
Low Power design
paramount.
Migrating on-chip for
voice processing, RF
A/D sampling, etc.
Specialized cores that
optimize function/W.
Increasing need for SoC
integration (digital domain
receivers (DSP), -processor,
standard IO cores, etc.)
Large gate counts.
High reliability.
Minimal on-chip
analog.
Processor cores and
some specialized
functions.
Primarily SoC
Minimal on-chip
analog.
MEMs for optical
switching.
Processor cores, FPGA
cores, and some
specialized functions.
Primarily SoC
Increased requirement
for higher precision
position measurement
and "inertia
knowledgeable"
actuator power
controllers integrated
on-chip.
Use of MEMs on R/W
head for sensing.
Increased demand for
high-speed hardware
for functions such as:
- "look-ahead" for
database search
- P instruction prefetch
- data compaction,
- signal to noise
monitoring
- failure prediction
- etc.
Large gate counts.
High reliability.
Reprogramability.
Increased use of large
FPGA to
accommodate current
custom functions.
Shift toward large
FPGA and full
supported vendor tool
sets, away from ASIC
costs and design
flows.
High-speed front-end
for storage systems.
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IC Product Domain
Mainly ASSP
EDP '2001
Market Drivers
Market Drivers
V. Consumer
1. Cost: asymptotic down
2. Time to Market: <12 mo.
3. Function: high novelty
4. Form factor
5. Durability / safety
6. Conservation / Ecology
VI. Computer
1. Speed: 10X every 10 years
2. Memory: 2X every 2 years
3. Power: Flat to decreasing
4. Form factor: Shrinking size
VII. Automotive
1. Functionality
2. Ruggedness (external environment)
3. Reliability / safety
4. Cost
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ASIC
For high-end products
only.
Possible
Reprogramability.
Increased demand for
digital capacity - high
gate count, highspeed.
Primarily for
entertainment
systems.
Analog
Custom
Major design realm.
Increased integration
of analog resulting
from voice, visual,
tactile and physical
measurement
("communicating
sensors” for
proximity, motion,
positioning).
CCD or CMOS
sensing for cameras.
Minimal.
Simple A/D & D/A
incorporation.
Video interfaces for
automated camera
monitoring, video
conferencing.
Integrated high-speed
A/D, D/A for
automated
instrumentation
monitoring and
logging, and rangespeed-position
resolution.
Shifting to DSP for
voice, visual and
physical measurement
("communicating
sensors” for
proximity, motion,
positioning).
MEMs for sensors.
For "long-life" mature
products only.
Decreased interest in
long design
cycles/high cost nonprepackaged
functions or design
flows.
Mainly ASSP
Increasingly SoC for high-end
digital using cores such as:
- 3d graphics
- CPU/MMU/DSP
- Voice synthesis
- Voice recognition
- RTOS kernels
- Parallel processing
- etc.
Processor cores and
some specialized
functions.
Increase in industry
partnerships on
common designs to
reduce development
costs requiring
ability to share data
and reuse across
different design
systems.
Primarily SoC - integration of
custom off-the-shelf P and I/O
cores.
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IC Product Domain
Mainly ASSP.
Increasingly SoC for high-end
using standard hardware
platforms with real time OS
kernel and embedded software.
EDP '2001
1997 NTRS
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1999 ITRS
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