Transcript No Slide Title

CS/EE 3700: Fundamentals of
Digital System Design
Chris J. Myers
Spring 2000 - 2001
Course Information
• Class webpage:
– www.async.elen.utah.edu/~myers/ee3700
• Get handout #1 for class and contact info.
• Class webboard – see the webpage
TAs and Grader
• Teaching assistants:
– David Sanderson
– Jian Zhou
– James Bergstrom
• Grader
– Dong-Hoon Yoo
• Lots of office hours, see handout #1.
Discussion Sections
• You must signup for and attend one
discussion section.
• Supplemental material given here to help
with homework and labs.
• Written assignments will be returned in
your discussion section.
• Sections start Wednesday.
Course Description
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Boolean algebra – theory for digital design.
Overview of implementation technology.
Combinational logic design.
Number representations and arithmetic.
Sequential logic design – sync and async.
VHDL and CAD tools utilized throughout.
Prerequisites
• Computer programming (CS 2010)
• PHYCS 2220
Textbook
• Fundamental of Digital Logic with VHDL
Design – by Brown and Vranesic, 2000.
Homework/Labs/Projects
• Homework/lab/project writeups should be turned
in to appropriate EE locker.
• Put discussion section number and TA on all
assignments.
• Hardware labs checked in discussion
section/office hours.
• Homework returned in your discussion section.
• All grading disputes must be made within one
week of receiving the grade.
Late Homework/Cheating
• No late homework/labs/projects will be
accepted.
• Cheating will be not be tolerated and it will be
strongly dealt with. This includes:
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Passing off someone else’s hardware as yours.
Copying someone else’s VHDL code.
Copying someone’s homework/exam answers.
etc.
Lab Kits
• Many labs will use lab kits.
• These include numerous chips, boards,
wires, and design tools.
• Distributed during first discussion section.
Grading Policy
• Homework and Labs – 30 percent
• Midterms – 30 percent
• Project – 20 percent
– A simple microprocessor
• Final – 20 percent
– Tuesday, May 1st, 7:00-9:00am
CS/EE 3700 : Fundamentals of
Digital System Design
Chris J. Myers
Lecture 1: Design Concepts
Chapter 1
Chip Complexity
• 1963: transistor size = 50m
1mm
4 km
MEB
Ft. Douglas
Chip Complexity
• 1975: transistor size = 10m
100 km
5mm
Salt Lake
Provo
Chip Complexity
• 1985: transistor size = 2m
10mm
1000 km
NV
UT
Chip Complexity
• 1995: transistor size = 0.4m
15mm
7500 km
North
America
SIA Roadmap
YEAR
1999
2001
2003
2006
2009
2012
xtor size
(m)
xtor/cm2
(million)
0.14
0.12
0.10
0.07
0.05
0.035
14
16
24
40
64
100
Chip size
(mm2)
800
850
900
1000
1100
1300
Figure 1.1
A silicon wafer
Standard Chips
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Realize common logic functions.
Usually less than 100 transistors.
Many common ones found in your lab kits.
You will use them in a couple of labs.
Not used much today as they occupy too
much space on printed circuit boards (PCB).
Programmable Logic Devices
• They can realize much more complicated
logic circuits than a standard chip.
• Often reprogrammable.
• Field-programmable gate arrays (FPGA)
will soon use more than 100 million xtors.
• Widely used today.
• You will use in one lab and your project.
Group of 8 logic cells
Memory block
Interconnection
wires
Figure 1.2
A field-programmable gate array chip
Custom-designed Chips
• PLDs are not very efficient so they may not
meet performance or cost objectives.
• May need to design a custom or semicustom chip (also known as an ASIC).
• Advantage: optimized for given task.
• Disadvantage: more complex design and
manufacturing process.
• Custom VLSI design taught in CS/EE 5710.
T itle:
(c omtest1.ps )
Creator:
(ImageMagic k)
Preview:
T his EPS pic ture was not s aved
with a preview i nc luded i n i t.
Comment:
T his EPS pic ture wi ll pri nt to a
Pos tScri pt printer, but not to
other types of printers.
Required product
Design specifications
Initial design
Simulation
Design correct?
Redesign
No
Yes
Prototype implementation
Make corrections
Yes
Testing
Minor errors?
Meets specifications?
Yes
Finished product
Figure 1.3
The development process
No
No
Design concept
Initial design
Simulation
Design correct?
Redesign
No
Yes
Successful design
Figure 1.4
The basic design loop
Figure 1.5
A printed circuit board
Design concept
A
Partition
B
Design one block
Design one block
C
Design interconnection between blocks
Functional simulation of complete system
Correct?
No
D
Yes
Physical mapping
Timing simulation
Correct?
Yes
Implementation
Figure 1.6
Design flow for logic circuits
No
Implementation
Build prototype
Testing
Modify prototype
Yes
No
Correct?
Minor errors?
No
Yes
Finished PCB
Figure 1.7
Go to A, B, C, or D in Figure 1.6
Completion of PCB development
Theory and Practice
• Numerous CAD tools available for design.
• Why study the theory and not just the tools?
– Designer must provide good specification.
– This theory is utilized in these tools, and it
helps you understand what the tools do.
– Designer must understand the effects of
optional processing steps.
– It is intellectually challenging.