Transcript Document

MODERN ENIAC T2.5 Review
Meeting
WP2 and Tasks review
Milano Agrate, 2011 Oct. 05
Meeting hosted by Micron
13:00 – 16:00 pm
WP2 Review Meeting
Milano, Oct 05, 2011
18/07/2015
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WP2 Domain and Technology overview per task and partner
Technologi
es
Process
simulation
Device
simulation
Electrical
Charact.
Reliability
Compact
Modeling
Task
2.1
2.2
2.3
2.4
2.5
Planar CMOS
65nm
UNCA
45nm
UNGL POLI
SNPS (STF2)
IMEP STF2
32nm
UNGL POLI
(STF2)
IMEP STF2
41nm
UNET NMX
SNPS
UNET NMX
FDSOI
IMEP (STF2)
LETI IMEP
Finfets, MUG,
GAA
STF2
NXP
NVM
UNGL
UNGL POLI
STF2 NXP
UNGL STF2
UNET (NMX)
UNET NMX
LETI
IMEP
HVMOS
AMS TUW
AMS TUW
AMS TUW
SiC,
Power MOS
STI
STI
STI
AlGaN-GaN
HEMT
STI
STI
STI
PV aware tools and methods are of common interest; they are developped and applied to a wide spectrum of
technologies (Project book rev2 v2.4.1).
Significant communalities of technology targets, except different ones for Process and Device simulation.
(not funded)
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T2.5 Task (2/1)
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Task T2.5: PV-aware compact modelling
PV and reliability effects have to be implemented in device compact models to be able to
accurately describe the impact of variability on circuit operation. Implementation methodologies
will be worked out and adopted in standard compact modeling.
Partners: UNET, AMS, LETI, NMX, NXP, POLI, STF2, ST-I, UNGL
UNGL will develop compact model parameter extraction strategies that capture accurately the
statistical device variability and the statistical aspects of reliability in industrial standard compact
models including BSIM, BSIMSOI and PSP. POLI will be developing PV aware compact models
in conjunction with the activities carried out in task 2.2, on the basis of the so-called sensitivity
approach. The approach will be exploited for the development of quasi-static models (through the
implementation of the DC sensitivity concept) and of dynamic models (through the implementation
of the large-signal sensitivity concept). The strategy allows very efficient compact models, also
accounting for the PV statistics, to be developed, also taking into account the correlation between
different input parameters, provided that the input statistics is modelled in closed form. Such
models will be deriving their parameters from physics-based simulations or characterizations. The
modelling strategy will be mainly applied to the CMOS 45/32nm process, but can be taken into
consideration for other technologies like GaAn/AlGaN power or RF devices as well. The compact
models will be implemented within the framework of a suitable circuit simulation platform.The aim
of the activity of ST-I is to develop a statistical Spice model for the design of complex nano-scale
IC starting from TCAD simulations directly linked to process fluctuations due to equipments
specifications. In this flow numerical techniques will be introduced in order to reduce the number
of technology CAD simulations to be performed to extract the statistical model of a single device
fabrication process and as consequence to reduce the computational costs and the time
consumed; at the same time techniques will be used to reduce the number of circuit simulations
for extraction of the statistical spice model of the IC, taking advantage of multi-objective
optimization algorithm for yield analysis in addition AMS will implement reliability effects in device
state of the art compact models in order to describe PV for circuit simulation in 0.35um, 0.18um
and 0.13um CMOS and HV technologies.
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T2.5 Task (2/2)
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Task T2.5: PV-aware compact modelling (cont’)
STF2 will focus on the compact modelling of PV effects in bulk CMOS technology and application
to the simulation of 45nm devices for circuit design. The work goes through classification of
variability relevant sources, development of a formal description of process/device variables and
associated compact models extensions in order to allow Monte-Carlo circuit simulation. The
compact model extensions derived are intended to reflect systematic and random effects
observed in a 45nm core CMOS technology at local scale (mismatch), intra-die scale, and
interdie, and their layout dependence. NXP’s contribution will address a realistic physics based
implementation method to mimic process variations as well as device fluctuations in analog circuit
simulation using the PSP compact model. This will initially be done for all device types in a
relatively mature 45nm CMOS node using the standard bulk CMOS PSP model. Subsequently,
the methodology will be ported, adjusted and refined to more advanced 40-32 and possibly 22nm
bulk CMOS nodes. With further scaling it becomes mandatory to come up with viable analytical
modeling approaches to efficiently incorporate new physics phenomena and their fluctuations in
compact models, including quasi ballistic transport (QTB) features and the impact of variations of
the dielectric thickness, channel doping and stress conditions, and with viable compact modeling
approaches to reach the best trade-off between accuracy and statistics, including variability.
UNET will address these aspects involving new physics for 45/32nm CMOS and for non-volatile
memory technologies. NMX will in this task study a viable and effective implementation of an
analytical compact model which takes into account PV in NVM logic devices (implementation of
the characterization performed in WP2.3) and the impact random dopant, edge roughness, and
trap position on scaled NVM cells; joint activities together with UNET are planned. Collaborations
with ST-I and NMX are envisioned. Starting from BSIMSOI and an in-house PSP modified thin film
device model, LETI will develop statistical modeling of the correlations between model parameters
and variability sources for the FDSOI 22nm technologies. This will be used to classify and quantify
FDSOI variability sources.
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Compact Modeling: T2.5 Deliverables
Goal: focus of Task 2.5 “PV-aware Compact Modeling” is to implement PV and
reliability effects in device compact models to be able to accurately describe the
impact of variability on circuit operation (UNET, AMS, LETI, NMX, NXP, POLI, STF2,
ST-I, UNGL.
Ref
Deliverable/ Contributors
Due date
D2.5.1
PV-aware circuit-level models for standard CMOS technologies (down to
45nm) (UNGL, UNET, NXP, POLI, ST-I, STF2) , and Non-Volatile-Memory
technologies (NMX, UNET), and Discrete Power Device,SiC, GaN/AlGaN
technologies (ST-I). State-of-the-art based statistical models, based on
hardware and/or TCAD
M18
D2.5.2
Statistical PV-aware models for planar bulk CMOS generation devices
(down to 32nm) (POLI, UNGL, UNET, NXP, AMS)
M30
In progress
D2.5.3
PV-aware circuit-level models for 45nm analog 32nm CMOS technology
(ST-F2)
Modeling of additional variability sources of 3-dimensional device
architectures, for new device architectures for 22nm (LETI, UNGL, UNET)
M33
Request
for change
(STF2)
Task Leader: [email protected]
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Done
D2.5.2 activities in progress
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D2.5.2 (M30)“Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm)
(POLI, UNGL, UNET, NXP, AMS)”
– Some partners already active (POLI, UNGL, UNET)
– POLI will carry on PV aware compact modeling in conjunction with the activities carried out in T2.2
(on the basis of the sensitivity approach)
• extend to 32nm process
– UNGL will
• create statistical compact model extraction strategies based on the comprehensive statistical
simulation carried out in D2.2.4
• investigate the sensitivity of compact model parameters for statistical compact model
extraction
• investigate the accuracy of compact model parameters as a function of the statistical
parameter set.
• apply PCA for width dependence of statistical parameter generation.
– UNET
• has already completed and reported work on strain with NXP (paper at IEDM)
• will develop fast and efficient models for new physical effects in advanced MOSFETs (quasi
ballistic transport)
• will work on Q.B.Transport with NXP
• Extremely efficient model for backscattering in nanoscale MOSFETs (elastic and inelastic)
• Fully calibrated and verified against Multi-Subband Monte Carlo simulations
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D2.5.2 - summary
WP2 Review Meeting
Milano, Oct 05, 2011
18/07/2015
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T2.5 publication list
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JOURNAL PAPERS
N. Serra and D. Esseni, “Mobility Enhancement in Strained n-FinFETs: Basic Insight and Stress Engineering”, IEEE
Transactions on Electron Devices, Vol.57, NO.2, pp.482-490, February 2010
A. Paussa, F. Conzatti, D. Breda, R. Vermiglio, D. Esseni and P. Palestri, “Pseudospectral methods for the efficient
simulation of quantization effects in nanoscale MOS transistors”, IEEE Transactions on Electron Devices, Vol. 57,
NO. 12, pp. 3239-3249, December 2010
CONFERENCES
J.-L.P.J. van der Steen, P. Palestri, D. Esseni and R.J.E. Hueting, “A New Model for the Backscatter Coefficient in
Nanoscale MOSFETs”, European Solid-State Device Research Conference (ESSDERC), Siviglia (ES), 13-17
settembre 2010, pp. 234-237
A. Paussa, F. Conzatti, D. Breda, R. Vermiglio, D. Esseni, "Pseudo-Spectral Method for the Modelling of
Quantization Effects in Nanoscale MOS Transistors", Proceedings International Conference on Simulation of
Semiconductor Processes and Devices (SISPAD), Bologna (Italia), settembre 2010, pag. 299-302
Workshops
SISPAD workshop on Statistical Variability (UNGL)
2010, 2011 VARI workshop Montpellier
L. Masoero, F. Bonani, F. Cappelluti, G. Ghione, “Modeling the effect of position-dependent random dopant
fluctuations on the process variability of submicron channel MOSFETs through charge-based compact models: a
Green's function approach” , Proc. VARI, Montpellier, 2010
F. Bertazzi, F. Bonani, S. Donati Guerrieri, G. Ghione, "Physics-BasedSmall-Signal Sensitivity Analysis for the
Variability Aware Assessment ofDevices and Linear Analog Subsystems", Proc. VARI 2011, Montpellier, May2011.
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Task Review Summary
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Activity done so far, with highlights on technical results, and dissemination
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Plan for next deliverables:
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no reply from some partners. Need to find more efficient « communication channels »
Interaction need
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D2.5.2 is almost ready. Waiting for one more contribution (ask Ghione)
D2.5.3 due at M33: it seems on track
Issues
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Variability-aware Compact Models for Si CMOS and NVMs (parameter extraction and
sensitivity evaluation)
Statistical models for specific physical mechanisms (development and calibration)
Improve communications. Maybe check the contact list and indentify also some « active
contributors » and not only « project contacts »
List of papers and workshops updated
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Little changes.
Remind to acknowledge MODERN
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CONTACT LIST T2.5 – before update
T2.5
Task leader
Paolo Pavan
UNET
[email protected]
Task participants
Alexander Steinmair
AMS
[email protected]
Jean-Rene Lepequeys
LETI
[email protected]
Paolo Fantini
NMX
[email protected]
Hans Tuinhout
NXP
[email protected]
Giovanni Ghione
POLI
[email protected]
Andre Juge
ST-F2
[email protected]
Valeria Cinnera
ST-I
[email protected]
Angelo Ciccazzo
ST-I
Giuseppe Privitera
[email protected]
[email protected]
Asen Asenov
UNG
[email protected]
Gareth Roy
UNGL
[email protected]
David Reid
UNGL
[email protected]
Campbell Millar
UNGL
[email protected]
WP2 Review Meeting
Milano, Oct 05, 2011
18/07/2015
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T2.5 back-up slides
WP2 Review Meeting
Milano, Oct 05, 2011
18/07/2015
11
D2.5.2: UNGL contribution
• Statistical compact modelling (SCM)
strategy featuring all variability sources is
developed for variability-aware compact
models in 32nm RVT N/PMOS.
• Direct extraction method based on
statistical physical simulations is
presented.
• Statistical model generation is developed
for large-array circuit simulation.
SCM first-step: uniform model
0.0012
0.0005
VD=1.0V
Simulations
BSIM4
0.0008
0.0006
0.0004
VD=0.05V
0.0002
0
0
0.2
0.4
0.6
0.8
0.0003
0.0002
VD=-0.05V
0.0001
0
0
1
0.2
VG (V)
Simulations
BSIM4
0.0004
|ID| (A/mm)
ID (A/mm)
0.6
0.8
1
0.0005
VG=1.0V
0.0008
VG=0.8V
0.0006
0.0004
VG=0.6V
0.0002
VG=0.4V
0
0
0.4
-VG (V)
0.0012
0.001
VD=-1.0V
Simulations
BSIM4
0.0004
|ID| (A/mm)
ID (A/mm)
0.001
0.2
0.4
0.6
VD (V)
0.8
VG=-1.0V
Simulations
BSIM4
VG=-0.8V
0.0003
0.0002
VG=-0.6V
0.0001
VG=-0.4V
1
0
0
0.2
0.4
0.6
0.8
1
-VD (V)
Uniform compact model is the base for statistical extraction,
requiring expertise and experience.
SCM second-step: statistical extraction
Identified parameters for extraction
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Possible selections of parameters
Vth0 – Threshold voltage of long• 1 parameter – Vth0
channel MOSFET
• 2 parameters – Vth0, U0
U0 – Low field mobility parameter.
• 4 parameters – Vth0, U0, Nfactor,
Nfactor – Subthreshold swing factor.
Voff
Voff – Offset voltage in
• 6 parameters - Vth0, U0, Nfactor,
subthreshold region for large W and
Voff, Vsat, and Dsub
L.
• 7 parameters – Vth0, U0, Nfactor,
Minv – Moderate inversion
Voff, Minv, Vsat, and Dsub
parameter.
Vsat – Related to saturation
velocity.
Select above parameters to extract
Dsub – DIBL coefficient in
statistical models from statistical
subthrethold region.
simulations based on uniform models
Statistical extraction (cont.)
0.4
0.4
1 parameter
2 parameters
4 parameters
6 parameters
7 parameters
0.2
0.1
0
0
1 parameter
2 parameters
4 parameters
6 parameters
7 parameters
0.3
Probability
Probability
0.3
0.2
0.1
10
20
30
RMS error (%)
NMOS
40
50
0
0
10
20
30
40
RMS error (%)
PMOS
More parameters to optimize, more accurate the model.
6 parameters extraction achieves almost the same accuracy
with 7 parameters.
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Statistical Model Generation
Statistical model generation (cont.)
NPM based on high moments demonstrates capability to
reproduce non-Gaussian distributed parameters.
Comparison of reproducing parameters
D2.5.3: Planned UNGL contribution
• Discover methods for extracting compact models
form the novel devices studied in D2.2.5
• Attempt to use the methodology used in D2.5.1
and D2.5.2 to extract statistical compact models
fro the Novel device Architectures
D2.5.3: UNGL Progress
Using BSIM Multi Gate the
characteristics obtained
from D2.2.5 have been
replicated.
Working to build an
automated extraction
strategy to allow statistical
extraction
D2.5.3 ST contribution
• Goal: Statistical Compact Modeling methodology applied in 32nm
planar CMOS technology
– LP Mosfet devices
– Intradie variations: statistical random + systematic
• Status of progress:
Variability
TCAD
HW Electrical
Characterization
Compact Modeling
Statistical
UNGL
D224 (done)
STF2/IMEP
D233 (done)
UNGL D252
from TCAD (done)
STF2 D253
from HW (dec 2011)
Systematic
NA
STF2
D253 (in progress)
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STF2 D253
from HW (dec 2011)