Transcript A Fast Evaluation of Power Delivery System Input Impedance

A Fast Evaluation of Power Delivery System
Input Impedance of Printed Circuit Boards
with Decoupling Capacitors
Jin Zhao ([email protected])
Sigrity Inc. Santa Clara, CA 95051
Om P. Mandhana ([email protected]) Freescale
Semiconductor, Austin, TX 78729
October 2004
EPEP 2004, Portland Oregon
Content
• Introduction
• Applied Methodology
• Application Examples
• Conclusion
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Introduction
• A noise-free, stable power delivery system is
required for high speed system
• Hundreds of decoupling capacitors are placed on
PCB to satisfy the requirement
• Efficiently selecting and placing decoupling
capacitors on board is a critical task for power
integrity analysis and design
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Traditional Approach
IC
CKTs
On-die
Interconnection
Package or
Substrate
On-die
Decaps
On-package
Decaps
•
Whole system has been represented as
multi-stage lumped circuits
•
As frequency increases, the wave
propagation effects within the board
structure must be considered in the
analysis and design of a PDS
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Printed Circuit Board
EPEP 2004, Portland Oregon
VRM
on
PCB
On-board
Decaps
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Applied Methodology
IC
CKTs
On-die
Interconnection
Package or
Substrate
On-die
Decaps
On-package
Decaps
Printed Circuit Board
VRM
on
PCB
On-board
Decaps
Lumped
Circuit
model
Multiple port network
Representing
Printed Circuit Board
Traditional approach
New approach
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Applied Methodology (cont)
Real physical board with pre-selected
locations of VRM, decoupling capacitors,
and interested IC chip locations
Commercial
Field Solver
Multiple ports corresponding to
VRM, decoupling capacitors and
interested IC chip locations
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Multiple port network
Representing
Printed Circuit Board
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Applied Methodology (cont)
Multiple port network
Representing
Printed Circuit Board
An impedance matrix can be
used to represent the network
V1   Z11
V   Z
 2    21
Multiple ports corresponding to VRM,     
decoupling capacitors and interested V   Z
 n   n1
IC chip locations
Z12
Z 22

Z n2
 Z1n   I1 
 Z 2 n   I 2 
    
 
 Z nn   I n 
These multiple ports can be divided
into two groups:
Ports with no termination (open), and
Ports terminated with loads
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Applied Methodology (cont)
Impedance matrix can be expressed as
For those ports terminated with a loading, one has
The resultant input impedance matrix (at the IC locations) can be
calculated as
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Applied Methodology (cont)
Challenges:
•
Involves large matrix inverse with several large matrix multiplications at every
frequency point
•
Very time consuming as the number of decoupling capacitors placed on board
increases
•
As the impedance of a decoupling capacitor, which depends on the
capacitance (C), equivalent series resistance (ESR) and equivalent series
inductance (ESL), is included in the matrix operations, ITERATIVELY selecting a
decoupling capacitor of appropriate C, ESR and ESL to optimize the power
delivery system performance becomes a time consuming process.
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Applied Methodology (cont)
Admittance Matrix Approach
The power ground admittance matrix with some decoupling capacitors
mounted on board can be easily calculated by adding the admittance of
the decoupling capacitor to the corresponding diagonal entry in the
original power ground admittance matrix without any decoupling
capacitors mounted on board
If no decoupling capacitor mounted at a port, the corresponding entry in the second matrix is 0.
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Application Example
A six layer printed circuit board
U17
Edge Connector
For board power supply
There are 0.22uF x 8 decoupling capacitors mounted on the upper side
There are 0.01uF x 20 and 0.1uF x 8 decaps mounted on the lower side
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Application Example (cont)
Upper side of the board, U17 is the interested location of power and ground.
C21~C28 are eight 0.22 uF decoupling capacitors mounted on board.
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Application Example (cont)
Lower side of the board, C1~C20 are twenty 0.01 uF decoupling capacitors,
C29~C36 are eight 1.0 uF decoupling capacitors mounted on board.
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Application Example (cont)
2
10
1
Impedance Magnitude (Ohm)
10
0
10
-1
10
-2
10
-3
10
0
1
2
3
4
5
Frequency (Hz)
6
7
8
9
10
8
x 10
Input impedance with and without decoupling capacitors mounted on board
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Application Example (cont)
2
10
1
Impedance Magnitude (Ohm)
10
0
10
-1
10
-2
10
From
From
From
From
-3
10
0
1
2
3
Commercial Software, with all decaps on board
Commercial Software, without any decaps on board
Matrix Computation, eqn (1) and (2), with all decaps on board
Matrix Computation, eqn (1) and (2), without any decaps on board
4
5
Frequency (Hz)
6
7
8
9
10
8
x 10
Input impedance obtained from commercial software and admittance approach
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Conclusion
• A fast power ground input impedance evaluation methodology
for the printed circuit board with decoupling capacitor placement
study is presented.
• The admittance approach can accurately estimate the power and
ground input impedance up to gigahertz frequency range, which
is typically high enough for board level power delivery system
analysis and design with targeting of decoupling capacitor
placement study.
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EPEP 2004, Portland Oregon
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