Transcript Document

CMOS for next 15 years as the mainstream
of nano device technology:
problems, solutions and beyond that
Tokyo Institute of Technology, Japan
Hiroshi IWAI
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Now: After 45 Years from the 1st single MOSFETs
16Gb NAND,
SAMSUNG
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Sub-10 nm CMOS transistors will be realized with new technologies
anyway.
Concerns of integration such huge number of transistors.
Already 16Gbit: larger than that of world population
comparable for the numbers of neurons
in human brain
128Gbit: comparable with those of galaxies
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Concerns for the integration
1) Too huge power consumption, heat generation?
2)Too huge variations in transistor characteristics, which could
make the circuit design impossible?
3)Too many number of transistors for the circuit designers to
manipulate? (design crisis)
4)No merit of transistor downsizing in performance and power,
because of CR of interconnect cannot be reduced?
8)Who will pay the huge production cost?
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Problem is the huge production cost and investment!
Amount of capital investment on Each of DRAM generation
Amount of capital investment (M US$)
2,000
300mm
wafer
1,800
Front-end
processing
equipments
Front-end
processing
buildings
1,600
1,400
1,200
200mm
wafer
1,000
800
600
Front-end
ancillary
facility
Back-end
processing
equipments
150mm
wafer
400
Back-end
processing
buildings
200
0
1M
4M
16M
64M
256M
1G
JEITA IC Handbook
Bit DRAM
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Examples of foundry facility: UMC
UMC
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Volume production with lager wafer is a solution
TSMC
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Concerns for Nano-CMOS
integration
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When do we start planning for next wafer size
transition?
200mm/1990
We are here
When does this
happen?
300mm/2001
450mm/2012?
(125/150mm - 1981)
9 yrs + 2 yrs delay*
9 yrs? + 2 yrs delay?
675mm/2021?
9 yrs + ?yrs delay
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Crystal pulling furnace becomes too huge
Si crystal height cannot be very long because of its weight
Furnace
 Height: 12 m
 Weight: 36 ton
 Hot zone: 40 inch
 Cusp-type super conductive magnet
Crystal
 Diameter: 400 mm
 Weight: over 400 kg
 Body length: over 1m
Provided by Super Silicon Crystal
Research Institute Corp.(SSi)
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There is a proposed time line from 300 to 450 mm,
but huge cost, work, energy are required,
And no one can take a leadership at this moment.
2004
2005
2006
2007
2008
2009
2010
2011
2012
2009
2010
2011
2012
Interoperability Testing
& Reliability Verification
Factory Control
System Standards
Direct Transport
Standards
Production Equipment
Standards
450mm wafer
Standards
Carrier & lot-size
determination
2004
2005
2006
2007
2008
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Concerns for the integration
1) Too huge power consumption, heat generation?
2)Too huge variations in transistor characteristics, which could
make the circuit design impossible?
3)Too many number of transistors for the circuit designers to
manipulate? (design crisis)
4)No merit of transistor downsizing in performance and power,
because of CR of interconnect cannot be reduced?
8)Who will pay the huge production cost?
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Those concerns have been talked about so many times and so
many years. (Like wolf boy!)
Hopefully, the status in which wolf has not come, would
continues for future.
Each concern is a really crisis and critical problem.
However, each crisis will not make completely useless to make
downsizing.
We will find a practical solution with many compromises, such
that water always fine a lowest places and keep running.
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Microprocessors Trend
Past: 1972 (Intel) Today: 2002 (Intel) 2008 (Intel)
Lg sub-25 nm
Lg sub-70 nm
Lg 10,000 nm
Tox 0.7 nm
Tox 1.4 nm
Tox 1200 nm
f 0.00075 GHz
f 2.53 GHz
f 30 GHz
P a few 100 mW
P several 10 W
P 10 kW
N 2.25k
Heat generation
N 50 M
N 1.8B
Increase in
Power consumption
Heat generation
MIPS 1M MIPS (TIPS)
2002年
10W/cm2 Hot plate
2006年
2010年
2016年
100W/cm2 Surface of nuclear reactor
1000W/cm2 rocket nozzle
10000W/cm2 Sun surface
P. P. Gelsinger, “Microprocessor for the New Millennium: Challenges,
Opportunities, and New Frontiers,” Dig. Tech. 2001 ISSCC, San Francisco,
pp.22-23, February, 2001
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1)Power and heat increase
Maybe, it is not efficient to increase the clock frequency and
number of transistors
There will not be a big merit without improving the operating
frequency of board or package, and reduce the power consumed
there.
Main job of my PC is editing of the document and accessing to
internet. Such an extremely high clock frequency should not be
necessary.
Improvement of PC algorithm such that using file searching
method of Google will save the power very much.
Downsizing of Printed Circuit Board will also save the power.
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5) Variation of transistor characteristics
System and circuit design will assume such variation.
If too huge variation, Reconfigurable circuit and system desing
can avoid such transistors with huge variations. ECC（Error
Correction Code） will helps a lot.
Cannot suppress the variation under certain level, but we can
offer as many transistors as the designers want.
It is also important to use the larger device in the circuit,
depending on the usage.
Large gate are is useful to reduce the flicker noise.
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6)Desing crisis for human power
We could expect the progress of CAD.
Then, we can do only whatever we can design in that period
with the given manpower.
Multi-level system/circuit design, such as multi-core of
microprocessor will save the human power, for example.
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7) Interconnect R & C
It has been continuously said from 2 or 3 micron meter
generations that interconnects limit the downsizing. But
fortunately, it has never happened before.
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8)Huge development and production cost.
Leading edge company in memory, microprocessor, DSP,
foundry make huge profit.
They should cover the coat.
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40000
Revenue
35000
35000
Profit
30000
30000
（ B Yen）
25000
25000
Japanese maker
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20000
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JEITA;
IC Handbook
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Intel Samsung TI RunesusToshiba TSMC
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8)Huge development and production cost.
Leading edge company will pay the cost.
Otherwise they will drop off from the existent race, and the
competitor will be very happy.
2nd and 3rd tier companies could enjoy the reduced cost of the
development and production, but no big profit.
They cannot be too late to proceed to the downsizing, because
China will catch up soon.
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Future
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Post Scaling Issue
Gate length
Post scaling period
?
3 nm
2030
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Anyway, we will reach the downsizing limit in 15- 20 years.
It will not happen, suddenly:
“There is no downsizing from tomorrow and you do not need
to come to company from tomorrow”
Probably, period of each generation, or node will becomes
longer and downsizing eventually approaches to the limitation.
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After the limit of downsizing?
No, technology node change, and then, no design of new microprocessors?
Same lithography mask can be used for many years?
Same equipment can be used for many years?
2nd, 3rd companies and counties reach to make the most advanced
microprocessors with cheap cost?
Then, price of microprocessors and even equipments becomes extremely
cheap?
It will be a very good thing for microprocessor users. However, will it be a
very serious crisis for advanced countries and companies in semiconductor?
If there is no more downsizing, the semiconductor engineers will lose their
jobs?
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There are many jobs after the downsizing.
Technologies of the introduction of new material, new process,
new structure, will not be completed in 15 years.
Note that introduction of new materials usually take more than
10 years.
There are also other many works remain:
Hybrid integration, 3D integration, Miniaturization of board.
Efficient algorithm for system.
There would be a revolution for manufacturing process
Do we need big CR?
What would be a wafer in future? Is it the same as it is now?
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(Gate length etc）
Size
New Materials, New Process, New Structure（Logic, Memory)
Hybrid integration of different functional Chip
Increase of SOC functionality
3D integration of memory cell
3D integration of logic devices
Miniaturization of Interconnects on ＰＣＢ
(Printed Circuit Board)
5 nm ？
Low cost for LSI process
Revolution for ＣＲ，Equipment, Wafer
Saturation of Downsizing
Introduction of algorithm
of bio-system
Brain of insects, human
2020 ？
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Thank you
for your attention!
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