Transcript Electrical 2

Electrical Characteristics
of IC’s
Part 2
Last Mod: January 2011
Paul R. Godin
Input/Output Current
Elec2.2
Gate Currents
Digital Logic devices are constructed from analog components
which include a variety of transistors, resistors, diodes and other
semiconductors.
TTL devices, based on
transistors, rely on current flow to
sense the input logic. Current
flow between the output of one
device and the input of the other
device is required to switch the
transistors on or off. The action
of the transistors is what
determines the output logic state.
Elec2.3
Source and Sink
• Every logic device will either source or sink current.
– When the gate output is in a high state, it sources current.
Sourcing = provides current
– When the gate output is in a low state, it sinks current.
Sinking = receives current
– Gate inputs can either sink or source current, depending on
the level of the output attached to it.
Current entering a gate is + (sink)
Current exiting a gate is - (source)
Elec2.4
Source and Sink
Output sinks current in a low state
Output sources current in a high state
Elec2.5
Driving and Loading
• Driving gate: A gate that provides a logic level to other gates.
• Loading gate: A gate that receives a logic level from other gates.
Driving Gate
Loading Gates
Elec2.6
Input and Output Current
• IIL: Input Low Current. Current when input is in a low state.
• IIH: Input High Current. Current when input is in a high state.
• IOL: Output Low Current. Current when output is in a low state.
• IOH: Output High Current. Current when output is in a high state.
Elec2.7
Input and Output Current
Elec2.8
Typical Current Values
• 7400:
–
–
–
–
IIL:-1.6mA
IIH: 40A
IOL:16mA
IOH: -0.4mA
• 74LS00:
–
–
–
–
IIL:-0.4mA
IIH: 20A
IOL:8mA
IOH: -0.4mA
Elec2.9
Fanout
• Fanout is the number of load inputs that a driving gate is
capable of handling.
How many loading inputs are present?
Elec2.10
Fanout
IOH
1 mA
If:
• the maximum output current of the
driving gate is 1 mA, and
• each loading input requires 0.2 mA
The driving gate can supply current to
5 inputs ( 5 x 0.2 mA = 1 mA )
IIH
0.2 mA
IIH
0.2 mA
0.2 mA
Elec2.11
Fanout
IOL
0.7 mA
If:
• the maximum current of the driving
gate is 0.7 mA, and
• each loading input requires 0.1 mA
The driving gate can sink current for 7
inputs ( 7 x 0.1 mA = 0.7 mA )
IIL
0.1 mA
IIL
0.1 mA
0.1 mA
Elec2.12
Calculating Fanout
IOL
# gate_ inputs(low)
IIL
IOH
# gate_ inputs(high)
IIH
Elec2.13
Fanout Calculation
• Must calculate for BOTH output high and output low. Select
the worst-case condition. (Disregard the negative in the
calculation)
• Consider the 7404:
O utput_ L ow
O utput_ H igh
IOL  2 0mA
IOH  1mA
IIL  2mA
IIH  5 0A
IOL  IIL  2 0mA  2mA  1 0
IOH  IIH  1mA  5 0A  2 0
Worst-case = 10
Elec2.14
Fanout Exercise
Use the Texas Instruments specification sheets to determine
the following Fanout values:
• SN74AS04 to SN74LS08
• SN74S08 to SN74ALS04B
Elec2.15
Power
Elec2.16
Some Definitions
• Quiescent: output logic that is not changing (also known as static)
• Dynamic: output logic that changes (also known as switching)
•
•
•
•
VCC: TTL Supply Voltage
ICC: TTL Supply Current
ICCH: TTL Supply Current with all outputs high.
ICCL: TTL Supply Current with all outputs low.
•
•
•
•
•
VDD: CMOS Supply Voltage
VSS: CMOS Ground
IDD: CMOS Supply Current (static/quiescent)
IT: CMOS Supply Current (static and dynamic)
CPD: CMOS Internal Capacitance
Elec2.17
Power (TTL)
• Power = Voltage  Current = VCC  ICC
Vcc & Icc
Elec2.18
Device Input Current (TTL)
• With all the outputs = logic high
• Input current = ICCH specification
ICCH
1
1
1
Make the outputs logic
high by applying the
appropriate input logic
1
Elec2.19
Device Input Current (TTL)
• With all the outputs = logic low
• Input current = ICCL specification
ICCL
0
0
0
Make the outputs logic
low by applying the
appropriate input logic
0
Elec2.20
TTL Power Calculation
• Power = Voltage  Current = VCC  ICC
• If all gates are high:
– Pd = VCC  ICCH
– ICC = ICCH
• If all gates are low:
– Pd = VCC  ICCL
– ICC = ICCL
Assume Vcc = 5V, unless otherwise specified
Elec2.21
TTL Power Calculation
• However, if some of the gates are high and others are low:
N
N
P  VCC   H ICCH  L ICCL
N
 N



where N=number of gates
This formula looks complicated...let’s approach it differently
Elec2.22
Device input current (TTL)
• With some inputs high and some low
• Input current = ICC
ICC
1
0
In this example, ½ of the gates are
logic high, ½ are logic low.
Pd= Vcc(½@ICCH + ½ @ ICCL)
Pd= Vcc((0.5ICCH) + (0.5ICCL))
1
0
Elec2.23
Device input current (TTL)
In this example, ¼ of the gates are
logic high, ¾ are logic low.
ICC
1
0
Pd= Vcc(¼@ICCH + ¾@ ICCL)
Pd=Vcc((0.25ICCH) + (0.75ICCL))
0
0
Elec2.24
TTL Power Calculation
• With switching outputs, Duty Cycle must be taken into account.
• For a duty cycle of 50%:
 ICCL
I
P  VCC   CCH
2




• For a duty cycle other than 50%:
P  VCC  D C  ICCH   1  D C  ICCL 
Hint: Don’t study the equations...learn the process
Elec2.25
Device input current (TTL)
ICC
DC=25%
0
In this example, ¼ of the gates are at 25%
duty cycle, ¾ are logic low.
Pd= Vcc(¼@(0.25ICCH+0.75  ICCL) + (¾ @ ICCL))
Pd= Vcc((0.25(0.25ICCH+0.75ICCL) + (0.75ICCL))
0
0
Remember: A duty cycle of 25% means that the output is high for 25% of
the time (using ICCH), and low for 75% of the time (using ICCL).
Elec2.26
CMOS Power
• CMOS uses very little power in the static state (in the order of W).
• As switching increases (more dynamic), so does power
consumption. This is primarily due to capacitance.
• Power requirements also increase with ambient temperature. As
temperature increases, so does power consumption.
• Static power consumption for a B-Series gate  500W maximum
• Other families of CMOS have lower power consumption.
Elec2.27
CMOS Power Calculation
• Most CMOS specification sheets provide the
mathematical equation for calculating power
consumption.
• Care must be taken when utilizing the specification
sheet.
– Current is specified per gate or per IC package. Read carefully.
– Formulas may vary (example: 4011B compared to the 4027B)
– IDD is different from IT
• Generally:
IT (pac kage
)  (I / kH z)  f   IDD
IT (gate)  (I / kH z)  f   IDD / N
Elec2.28
End
January 2011
Paul R. Godin
prgodin @ gmail.com