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Chapter 1: Perspectives
Copyright @ 2005-2008 Yan Solihin
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of Parallel Computer Architecture, 2008”.
Outline for Lecture 1
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Introduction
Types of parallelism
Architectural trends
Why parallel computers?
Scope of CSC/ECE 506
Fundamentals of Computer Architecture - Chapter 1
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Key Points
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More and more components can be integrated on a
single chip
Speed of integration tracks Moore’s law, doubling every
18–24 months.
Exercise: Look up how the number of transistors per
chip has changed, esp. since 2006. Submit here.

Until recently, performance tracked speed of integration
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At the architectural level, two techniques facilitated this:
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Instruction-level parallelism
Cache memory
Performance gain from uniprocessor system was high
enough that multiprocessor systems were not viable for
most uses.
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Illustration
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100-processor system with perfect speedup
Compared to a single processor system
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Year
Year
Year
…
Year
1: 100x faster
2: 62.5x faster
3: 39x faster
10: 0.9x faster
Single-processor performance catches up in just a few
years!
Even worse
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It takes longer to develop a multiprocessor system
Low volume means prices must be very high
High prices delay adoption
Perfect speedup is unattainable
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Why did uniprocessor performance
grow so fast?
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≈ half from circuit improvement (smaller transistors,
faster clock, etc.)
≈ half from architecture/organization:
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Instruction-level parallelism (ILP)
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Pipelining: RISC, CISC with RISC back-end
Superscalar
Out-of-order execution
Memory hierarchy (caches)
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Exploit spatial and temporal locality
Multiple cache levels
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But uniprocessor perf. growth is stalling
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Source of uniprocessor performance growth: ILP
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ILP growth has slowed abruptly
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Parallel execution of independent instructions from a
single thread
Memory wall: Processor speed grows at 55%/year,
memory speed grows at 7% per year
ILP wall: achieving higher ILP requires quadratically
increasing complexity (and power)
Power efficiency
Thermal packaging limit vs. cost
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Types of parallelism
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Instruction level (cf. ECE 521)
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Pipelining
A (a load)
B
C
IF
ID
EX
MEM
WB
IF
ID
EX
MEM
WB
IF
ID
EX
MEM
WB
Fundamentals of Computer Architecture - Chapter 1
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Types of parallelism, cont.
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Superscalar/ VLIW
Original:
LD
F0, 34(R2)
ADDD
F4, F0, F2
LD
F7, 45(R3)
ADDD
F8, F7, F6
Schedule as:
LD
F0, 34(R2)
| LD
F7, 45(R3)
ADDD
F4, F0, F2
| ADDD
F8, F0, F6
+ Moderate degree of parallelism
– Requires fast communication (register level)
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Why ILP is slowing
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Branch-prediction accuracy is already > 90%
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Number of pipeline stages is already deep (≈ 20–30
stages)
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But critical dependence loops do not change
Memory latency requires more clock cycles to satisfy
Processor width is already high
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Hard to improve it even more
Quadratically increasing complexity to increase the width
Cache size
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Effective, but also shows diminishing returns
In general, the size must be doubled to reduce miss rate
by a half
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Current trends: multicore and manycore
Aspect
Intel
Clovertown
AMD
Barcelona
IBM Cell
# cores
4
4
8+1
Clock
frequency
2.66 GHz
2.3 GHz
3.2 GHz
Core type
OOO
Superscalar
OOO
Superscalar
2-issue SIMD
Caches
2x4MB L2
512KB L2
(private),
2MB L3 (shd)
256KB local
store
Chip power
120 watts
95 watts
100 watts
Exercise: Browse the Web for information on more recent
processors, and for each processor, fill out this form.
(You can view the submissions here.)
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Historical perspectives
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’80s – early ’90s: Prime time for parallel architecture
research
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A microprocessor cannot fit on a chip, so naturally need
multiple chips (and processors)
J-machine, M-machine, Alewife, Tera, HEP, DASH, etc.
Exercise: Pick one of these machines, and identify a
major innovation that it introduced. Submit here.
’90s: At the low end, uniprocessor systems’ speed
grows much faster than parallel systems’ speed
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A microprocessor fits on a chip. So do branch predictor,
multiple functional units, large caches, etc.!
Microprocessor also exploits parallelism (pipelining,
multiple-issue, VLIW) – parallelisms originally invented for
multiprocessors
Many parallel computer vendors went bankrupt
Prestigious but small high-performance computing market
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“If the automobile industry advanced as rapidly as the
semiconductor industry, a Rolls Royce would get a half
million miles per gallon and it would be cheaper to
throw it away than to park it.”
Gordon Moore,
Intel Corporation, 1998
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Historical perspectives, cont.
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’90s: Emergence of distributed (vs. parallel) machines
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Progress in network technologies:
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Network bandwidth grows faster than Moore’s law
Fast interconnection networks getting cheap
Connects cheap uniprocessor systems into a large
distributed machine
Network of Workstations, Clusters, Grid
’00s: Parallel architectures are back!
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Transistors per chip >> microprocessor transistors
Harder to get more performance from a uniprocessor
SMT (Simultaneous multithreading), CMP (Chip MultiProcessor), ultimately Massive CMP
E.g. Intel Pentium D, Core Duo, AMD Dual Core, IBM
Power5, Sun Niagara.
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Parallel computers
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A parallel computer is a collection of processing
elements that can communicate and cooperate to solve
a large problem fast. [Almasi & Gottlieb]
“collection of processing elements”
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How many? How powerful each? Scalability?
Few very powerful (e.g., Altix) vs. many small ones
(BlueGene)
“that can communicate”
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How do PEs communicate? (shared memory vs. messagepassing)
Interconnection network (bus, multistage, crossbar, …)
Metrics: cost, latency, throughput, scalability, fault
tolerance
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Parallel computers, cont.
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“and cooperate”
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Issues: granularity, synchronization, and autonomy
Synchronization allows sequencing of operations to ensure
correctness
Granularity up  parallelism down, communication down,
overhead down
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Statement/instruction level: 2–10 instructions (ECE 521)
Loop level: 10 – 1K instructions
Task level: 1K – 1M instructions
Program level: > 1M instructions
Autonomy
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SIMD (single instruction stream) vs. MIMD (multiple
instruction streams)
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Parallel computers, cont.
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“solve a large problem fast”
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General- vs. special-purpose machine?
Any machine can solve certain problems well
What domains?
 Highly (embarassingly) parallel apps
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Medium parallel apps
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Many scientific codes
Many engineering apps (finite-element, VLSI-CAD)
Not parallel apps
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Compilers, editors (do we care?)
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Why parallel computers?
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Absolute performance: Can we afford to wait?
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Folding of a single protein takes years to simulate on the
most advanced microprocessor. It only takes days on a
parallel computer
Weather forecast: timeliness is crucial
Cost/performance
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Harder to improve performance on a single processor
Bigger monolithic processor vs. many, simple processors
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Power/performance
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Reliability and availability
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Key enabling technologies
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Advances in microprocessor and interconnect technology
Advances in software technology
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Scope of CSC/ECE 506
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Parallelism
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Loop-level and task-level parallelism
Flynn taxonomy:
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SIMD (vector architecture)
MIMD
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Shared memory machines (SMP and DSM)
Clusters
Programming Model:
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Shared memory
Message-passing
Hybrid
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Loop-level parallelism
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Sometimes each iteration can be performed
independently
for (i=0; i<8; i++)
a[i] = b[i] + c[i];

Sometimes iterations cannot be performed
independently  no loop-level parallelism
for (i=0; i<8; i++)
a[i] = b[i] + a[i-1];
+
+
–
–
Very high parallelism > 1K
Often easy to achieve load balance
Some loops are not parallel
Some apps do not have many loops
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Task-level parallelism
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Arbitrary code segments in a single program
Across loops:
Subroutines:
…
for (i=0; i<n; i++)
sum = sum + a[i];
for (i=0; i<n; i++)
prod = prod * a[i];
…
Cost = getCost();
A = computeSum();
B = A + Cost;

Threads: e.g., editor: GUI, printing, parsing
+ Larger granularity => low overheads, communication
– Low degree of parallelism
– Hard to balance
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Program-level parallelism
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Various independent programs execute together
gmake:
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gcc
gcc
gcc
gcc
–c code1.c
// assign to proc1
–c code2.c
// assign to proc2
–c main.c
// assign to proc3
main.o code1.o code2.o
+ No communication
– Hard to balance
– Few opportunities
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Scope of CSC/ECE 506
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Parallelism
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Loop-level and task-level parallelism
Flynn taxonomy:
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SIMD (vector architecture)
MIMD
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Shared-memory machines (SMP and DSM)
Clusters
Programming Model:
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Shared memory
Message-passing
Hybrid
(Data parallel)
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Taxonomy of parallel computers
The Flynn taxonomy:
• Single or multiple instruction streams.
• Single or multiple data streams.

1. SISD machine (Most desktops, laptops)
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Only one instruction fetch stream
Most of today’s workstations or desktops
Control
unit
Instruction
stream
ALU
Data
stream
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SIMD
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Examples: Vector processors, SIMD extensions (SSE)
A single instruction operates on multiple data items.
SISD:
for (i=0; i<8; i++)
a[i] = b[i] + c[i];
SIMD:
a = b + c;
ALU 1
Control Instruction
unit
stream
ALU 2
ALUn
// vector addition
Data
stream
1
Data
stream
2
Data
streamn
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MISD
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Example: CMU Warp
Systolic arrays
Data
stream
Control Instruction ALU 1
unit 1 stream 1
Control Instruction ALU 2
unit 2 stream 2
Control Instruction ALUn
unitn
streamn
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MIMD
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Independent processors connected together to form a
multiprocessor system.
Physical organization:
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Determines which memory hierarchy level is shared
Programming abstraction:

Shared Memory:
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on a chip: Chip Multiprocessor (CMP)
Interconnected by a bus: Symmetric multiprocessors
(SMP)
Point-to-point interconnection: Distributed Shared
Memory (DSM)
Distributed Memory:

Clusters, Grid
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MIMD Physical Organization
P
P
Shared-cache architecture:
- CMP (or Simultaneous Multi-Threading)
- e.g.: Pentium 4 chip, IBM Power4 chip, Sun
Niagara, Pentium D, etc.
- Implies shared-memory hardware
…
caches
M
P
P
caches
caches
Network
M
…
UMA (Uniform Memory Access)
Shared Memory :
- Pentium Pro Quad, Sun Enterprise,
etc.
- What interconnection network?
- Bus
- Multistage
- Crossbar
- etc.
- Implies shared-memory hardware
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MIMD Physical Organization (2)
P
P
caches
caches
M
M
Network
…
NUMA (Non-Uniform Memory
Access)
Shared Memory :
- SGI Origin, Altix, IBM p690,
AMD Hammer-based system
- What interconnection network?
- Crossbar
- Mesh
- Hypercube
- etc.
- Also referred to as Distributed
Shared Memory
Fundamentals of Computer Architecture - Chapter 1
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MIMD Physical Organization (3)
P
P
caches
caches
M
M
I/O
I/O
Distributed System/Memory:
- Also called clusters, grid
- Don’t confuse it with distributed
shared memory
Network
Fundamentals of Computer Architecture - Chapter 1
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Scope of CSC/ECE 506
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Parallelism


Loop-level and task-level parallelism
Flynn taxonomy:

MIMD

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Shared memory machines (SMP and DSM)
Programming Model:



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Shared memory
Message-passing
Hybrid (e.g., UPC)
Data parallel
Fundamentals of Computer Architecture - Chapter 1
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Programming models: shared memory

Shared Memory / Shared Address Space:

Each processor can see the entire memory
P
P
…
P
Shared M

Programming model = thread programming in
uniprocessor systems
Fundamentals of Computer Architecture - Chapter 1
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Programming models: message-passing

Distributed Memory / Message Passing / Multiple
Address Space:

a processor can only directly access its own local
memory. All communication happens by explicit
messages.
P
P
M
M
P
P
M
M
Fundamentals of Computer Architecture - Chapter 1
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Programming models: data parallel

Programming model

Operations performed in parallel on each element of data structure
Logically single thread of control, performs sequential or parallel
steps

Conceptually, a processor associated with each data element

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Architectural model

Array of many simple, cheap processing elements (PEs) with little
memory each
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Processing elements don’t sequence through instructions
PEs are attached to a control processor that issues instructions
Specialized and general communication, cheap global
synchronization
Original motivation
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Matches simple differential equation solvers
Centralize high cost of instruction fetch/sequencing
Fundamentals of Computer Architecture - Chapter 1
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Top 500 supercomputers
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http://www.top500.org
Let’s look at the Earth Simulator
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Was #1 in 2004, #10 in 2006
Hardware:
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5,120 (640 8-way nodes) 500 MHz NEC CPUs
8 GFLOPS per CPU (41 TFLOPS total)
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30s TFLOPS sustained performance!
2 GB (4 512 MB FPLRAM modules) per CPU (10 TB total)
Shared memory inside the node
10 TB total memory
640 × 640 crossbar switch between the nodes
16 GB/s inter-node bandwidth
16 kW power consumption per node
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Exercise
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
Go to http://www.top500.org and look at the Statistics
menu in the top menu bar. From the dropdown,
choose one of the statistics, e.g., Vendors, Processor
Architecture, and examine what kind of systems are
prevalent. Then do the same for earlier lists, and
report on the trend. You may find interesting results
by clicking on “Historical charts”.
You can go all the way back to the first list from 1993.
Submit your results here.
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