Transcript CS 2204 Fall 2005 - NYU Polytechnic School of Engineering

CS 2204
Digital Logic
and
State Machine Design
As you wait for the lab to start :
Lab 4
Reserve seats for your partners
Experiment 1
Spring 2014

Experiment 1 Lab 4 Outline
 Presentation

Using A Brief Look at Semiconductor Technology
 Component selection for a new chip and a new PCB
 Semiconductor technology overview
• Gates, switches and digital electronic circuits
• Complementary Metal Oxide Semiconductor (CMOS) overview
• Transistor-Transistor Logic (TTL) overview

Using Term Project (pages 20 - 21)

Using Term Project Design Checks
 Analysis of the term project
• Digital Systems
• Analysis of Block 3 of the term project
 Digital Design Conventions
 Individual work


Experiment 1 is over three weeks : Labs 3, 4 and 5
 Develop a 4-bit 2-to-1 MUX of Block 2
• By using Handout 3 distributed in class
New handout
 Term Project Design Checks
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Today’s
work
Presentation
 Xilinx Project Development Steps

Develop the schematic
 Design the schematic
• Place the components and wires
 Do a schematic check
 Test the schematic via logic simulations

What are these
components ?
Do a Xilinx IMPLEMENTATION
 It maps the components to the CLBs of the chip
• Do timing simulations to test the schematic
 It generates the bit file

Download the bit file to the FPGA and test the design on the
board
 It programs the chip
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Developing a digital product
 A new chip

Which gates & FFs and how many is determined by
 Available components of technology chosen
 Besides the major operations and speed, cost, power, etc.
design goals of the digital product

FPGAs are used to test the new chip
 A new PCB

Which chips and how many is determined by
 Available chips of technology chosen
 Besides the major operations and speed, cost, power, etc.
design goals of the digital product
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 4

Developing a digital product
 A new chip
We will try to use high density components as
much as possible
 We will try not to use low-density components
(gates and flip-flops)

 We will work on chip design in the classroom
and in the lab

Lectures, homework assignments, exams and labs
CS 2204 Spring 2014 Experiment 1 Lab 4
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
CS2204 Components
 Available components for a new chip
Use these
Generic components
as much
as possible Lectures, homework, exams
Flip-flops Popular digital circuits
AND
D
OR
JK
NOT
T
NAND
SR
NOR
…
…
To save time,
space, power.
weight,…
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
High-density components
Gates
Xilinx components
Labs
Gates
AND
OR
NOT
NAND
NOR
…
Flip-flops
D
T
JK
Popular digital circuits
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
CS 2204 Spring 2014 Experiment 1 Lab 4
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
CS2204 Components
Lab design
 Available components for a new chip
Gates Flip-flops
AND
OR
NOT
NAND
NOR
…
D
JK
T
SR
Popular digital circuits
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
Xilinx components
Labs
Gates Flip-flops Popular digital circuits
AND
OR
NOT
NAND
NOR
…
D
T
JK
Try not to use
these components
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
CS 2204 Spring 2014 Experiment 1 Lab 4
High-density components
Generic components
Lectures, homework, exams
Use Xilinx macros
as much as possible
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
Developing a digital product
 A new PCB
We will try to use high density chips (MSI, LSI,
VLSI, ULSI) as much as possible
 We will try not to use low-density chips (SSI)

 We will work on PCB design in the classroom

Lectures, homework assignments and exams
CS 2204 Spring 2014 Experiment 1 Lab 4
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
CS2204 components
 Available chips for a new PCB
Use these Generic chips
as much
Lectures, homework, exams
as possible
Flip-flops Popular digital circuits
AND
D
OR
JK
NOT
T
NAND
SR
NOR
…
…
To save time,
space, power.
weight,…
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
High-density chips
Gates
TTL LS chips
Lectures, homework, exams
Gates
AND
OR
NOT
NAND
NOR
…
Flip-flops
D
JK
Popular digital circuits
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
CS 2204 Spring 2014 Experiment 1 Lab 4
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CS2204 components
 Available chips for a new PCB
Gates
AND
OR
NOT
NAND
NOR
…
Flip-flops Popular digital circuits
D
JK
T
SR
…
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
TTL LS chips
Lectures, homework, exams
Gates
AND
OR
NOT
NAND
NOR
…
Flip-flops
D
JK
Try not to use
these SSI chips
Popular digital circuits
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
CS 2204 Spring 2014 Experiment 1 Lab 4
MSI, LSI chips
Generic chips
Lectures, homework, exams
Use higher density chips
(MSI, LSI,…) as much
as possible
High-density chips

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
Digital circuits consist of gates and FFs
 FFs consist of gates
D FF implementation
via gates
D FF
From ON Semiconductor LS TTL Data Manual
 Digital circuits consist of gates !

Gates are on chips !
 Chips are on PCBs
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Gates are implemented by electronic components :
 Transistors, resistors, diodes, capacitors,…
74LS00
Quad
2-input
TTL
NAND
Gate
chip
From ON Semiconductor LS TTL Data Manual
NAND
TTL 2-input
NAND gate
implementation
via electronic
components
CMOS 2-input
NAND gate
implementation
via electronic
components
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Most Common Voltages for Logic Values
 Logic 1 is +5v
 Logic 0 is 0v
 The terminology


+5v  VCC
0v  GND (Ground)
 Xilinx Devices for voltages
VCC and GND are on the
Xilinx component list
CMOS 2-input
NAND gate
implementation
via electronic
components
2-input
NAND
gate
TTL 2-input NAND gate
ON Semiconductor
LS TTL Data Manual
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Transistors are the Main Electronic Component
 Transistors are used as switches to implement gates

A switch is open or closed based on the control input value :
0

Open when control is 0 :
1
0
1

Closed when control is 1
1
1
 The speed of switches determines the speed of the
electronic circuit, therefore, the gate
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Implementing AND gates
k
k
m
AND
k.m
m
1
k.m
AND gate
 Implemented by two switches connected in
series
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Implementing OR gates
k
k
m
OR
OR gate
k+m
1
k+m
m
 Implemented by two switches connected in
parallel
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Implementing NOT gates
k
k
NOT
k
1
1
NOT gate (inverter)
 Implemented by one switch
CS 2204 Spring 2014 Experiment 1 Lab 4
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
2-to-1 MUX Implementation
a
b
y(a, b, c) = a.b + a.c
1
a
a
c
NOT
b
AND
OR
c
a
AND
y(a, b, c) = a.b + a.c
A switching network
implementing
a gate network
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
The Gate Implementation
 Implementing gates is more complex than just connecting
switches (transistors) in series/parallel

A 2-input NAND gate implementation
 Resistors, diodes, etc. are used for reliable operation with TTL
technology
• Five transistors : Q1 – Q5, six diodes : D1 – D6 and seven resistors
 Multiple transistors are used for reliable operation with CMOS
technology
• A 2-input NAND gate implementation
• Four transistors
NAND
CMOS 2-input
NAND gate
implementation
via electronic
components
TTL 2-input NAND gate
ON Semiconductor
LS TTL Data Manual
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Electronic Components on the Chip
 All electronic components are placed in the
die area
The die of chip : area containing
transistors, resistors, diodes,…
Die
A chip
Intel Pentium 4 die
There are more than 225
million transistors on die
www.intel.com
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Die Fabrication Today
 Dice for the same chip type are placed on a wafer
Die
Intel Pentium 4 chip
Intel Pentium 4 die
From : Intel
Intel Pentium4 wafer
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
Gates have features
 Speed, Cost, Power, Size,…

Transistors, resistors,.. have features (device
characteristics)
 Speed, cost, power, size,..
 Device characteristics are determined by

The substance used for chips
 Silicon, Silicon Germanium, Gallium Arsenide

The transistor type
 Unipolar, bipolar

Electronic (transistor) circuits that form the gates
 CMOS, BiCMOS, TTL, ECL,…
Technologies
CS 2204 Spring 2014 Experiment 1 Lab 4
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
In order to study gate features
 Speed, Cost, Power, Size,…

We need to study substances, transistor
types and transistor circuits
 The technology chosen

CMOS, BiCMOS, TTL, ECL
 They have their own subfamilies
 CMOS : HC, HCT, AC, ACT, FCT,…
 TTL : H, L, S, LS, AS,…
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Substances
 Today’s chips use semiconductor substances

Silicon is the most common semiconductor substance
 Silicon is the slowest substance
Silicon
Silicon Germanium
(SiGe)
Unipolar
CMOS
Gallium
Arsenide
Niobium
(Superconducting)
(Not a semiconductor)
Transistor
type
Bipolar
BiCMOS
TTL
Substance
used
Transistor
circuit
ECL
SSI MSI LSI VLSI ULSI LSI VLSI ULSI SSI MSI LSI
SSI MSI LSI SSI MSI LSI
faster
Number of
gates on
the chip
Transistors were implemented by germanium, a semiconductor
Transistors are now implemented by silicon, another semiconductor
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Transistors
 Unipolar transistors are slower, but consume less
power
Silicon
Silicon Germanium
(SiGe)
Unipolar
CMOS
Gallium
Arsenide
Niobium
(Superconducting)
(Not a semiconductor)
Transistor
type
Bipolar
BiCMOS
TTL
Substance
used
Transistor
circuit
ECL
SSI MSI LSI VLSI ULSI LSI VLSI ULSI SSI MSI LSI
SSI MSI LSI SSI MSI LSI
faster
Number of
gates on
the chip
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Transistors Circuits
 CMOS circuits are slower, but consume less power
TTL chips are the most widely available
Silicon
Silicon Germanium
(SiGe)
Unipolar
CMOS
Gallium
Arsenide
Niobium
(Superconducting)
(Not a semiconductor)
Transistor
type
Bipolar
BiCMOS
SSI MSI LSI VLSI ULSI LSI VLSI ULSI
TTL
Substance
used
Transistor
circuit
ECL
SSI MSI LSI
SSI MSI LSI SSI MSI LSI
faster
Number of
gates on
the chip
More on gate features next week !
CS 2204 Spring 2014 Experiment 1 Lab 4
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 Silicon Technology Today
a)
Intel Poulson (Itanium)
8 cores
32 Mbyte L3 Cache
3.1 Billion transistors,
170 Watts
b)
c)
d)
e)
f) Today : Beyond ULSI Multichip module, MCM (>1 die on
chip), Giga Scale, etc.
(200M–7B transistors)
Will there be an end to shrinking the silicon transistor size ?
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Fan-in
 The maximum number of inputs a gate can
have
This is purely electrical
 Determined by the technology

 The electronic circuitry determines how many inputs to
have for reliable operation
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
Fan-out
 The number of gate inputs that can be connected to
a gate output


This is purely electrical
Determined by the technology
 CMOS gates have the best fan-out

If the fan-out is exceeded
 The output value may be noisy
 The output value may not be electrically “strong” to be
interpreted as 1 or 0
 The output can be physically damaged
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Fan-out
 In order to increase the fan-out buffers are used


Regular buffers (not input nor output buffers) are used to
increase the fan-out
A buffer is an electronic circuit that has no logic function !
 It transfers the input to the output with a delay !
 It also strengthens the electrical signal
 Some buffers are also labeled as drivers since they can
electrically “drive” large currents, hence drive many inputs
 Some buffers are designed so that they can filter noise on the
inputs
CS 2204 Spring 2014 Experiment 1 Lab 4
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Fan-out


Increasing the fan-out
a
b
y
c
Use a buffer !
But, the input to
output delay is
increased
.....
.....
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
Technology of components/chips
 Complementary Metal Oxide Semiconductor (CMOS)

Uses unipolar transistors
 Slower than Bipolar transistors
 Consume less power than Bipolar transistors

Not straightforward to connect to TTL chips
Silicon
Silicon Germanium
(SiGe)
Unipolar
CMOS
Gallium
Arsenide
Niobium
(Superconducting)
(Not a semiconductor)
Transistor
type
Bipolar
BiCMOS
SSI MSI LSI VLSI ULSI LSI VLSI ULSI
TTL
Substance
used
Transistor
circuit
ECL
SSI MSI LSI
SSI MSI LSI SSI MSI LSI
faster
CS 2204 Spring 2014 Experiment 1 Lab 4
Number of
gates on
the chip
Page 32

Complementary Metal Oxide Semiconductor
(CMOS)
 Low density commercial CMOS families, each with a
different combination of speed, power, cost
 4000 (Oldest)
 74HC (High speed CMOS)
 74HCT (High speed CMOS, TTL Compatible)
 74AC (Advanced CMOS)
 74ACT (Advanced CMOS, TTL Compatible)
 74FCT (Fast CMOS, TTL Compatible)
 74FCT-T (Fast CMOS, TTL Compatible with TTL
VOH)
 Most high-density chips

Microprocessors, GPUs, FPGAs, DRAMs, FlashEPROMs,..
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Complementary Metal Oxide
Semiconductor (CMOS)



CMOS chips consume very little power
Better Fan-out than TTL chips
CMOS chips are sensitive to static
electricity

One should not touch them

Unless properly grounded
• A wire strapped around the wrist is connected to
the ground
• The ground has 0v
CS 2204 Spring 2014 Experiment 1 Lab 4
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Complementary Metal Oxide Semiconductor (CMOS)


Unused gate input
1)
Do not leave it unconnected (floating)
a
y
b
?
Hi-Z value observed at the input
a
b
y
The gate will not work properly
Xilinx does not allow this option !

A No Driver warning is given by the Project Manager
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Digital Engineering Terminology
U1
U2
a
Must be
corrected
U4 input has no driver
U4 input is not
connected to an output.
Its input value is Hi-Z
(High-Impedance) as
there is infinite
impedance (resistance)
into the U4 input so no
current can flow in
U4
b
y
a
c
U3
CS 2204 Spring 2014 Experiment 1 Lab 4
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Complementary Metal Oxide Semiconductor
(CMOS)


Unused gate input
2) It can be tied to a used input
a
y
b

An available 3-input AND gate used
to implement a 2-input AND gate
The fan-out of the b signal may be exceeded !
CS 2204 Spring 2014 Experiment 1 Lab 4
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Complementary Metal Oxide Semiconductor (CMOS)


Unused gate input
3)
It can be connected to 1 or 0 depending on the gate type, via a
pull-up resistor or pull-down resistor
a
a
b
b
y
y
Pull-down
resistor
Pull-up
resistor
+5 v
0v
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Complementary Metal Oxide Semiconductor (CMOS)
 Gate output

Regular
Do not short circuit regular gate outputs
Xilinx warning message from
the Project Manager :
Multiple drivers on output y
y
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Digital Engineering Terminology
U1
U2
a
U4
b
y
a
c
U3
Must be corrected
Multiple drivers on output y
U3 and U4 outputs are short circuited
CS 2204 Spring 2014 Experiment 1 Lab 4
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Complementary Metal Oxide Semiconductor
(CMOS)

 Gate output

Tri-state outputs
 The output has three values !
• 1, 0 and Hi-Z ≡ High-impedance ≡ Floating ≡ Static voltage
• There is an extra control input, Enable, to enable/disable output
► If disabled, the output value is Hi-Z (high-impedance)
a
y
b
Enable
Tri-state symbol
Enable
y
0
Hi-Z
1
ab
Operation table
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 41

Complementary Metal Oxide Semiconductor (CMOS)
 Gate output

Tri-state outputs
 A tri-state gate can be envisioned as a regular gate with a switch at
the output
y
a
Output y has
three values
a
y
b
b
Enable
Regular gate
Enable
0
Switch
closed
Switch
open
1
CS 2204 Spring 2014 Experiment 1 Lab 4
Hi-Z
Page 42

Complementary Metal Oxide Semiconductor (CMOS)
 Gate output :

Tri-state gate outputs can be short circuited if only one gate is
enabled at a time
Enable1
You can short circuit
tri-state gate
outputs
y
Tri-state outputs are often
used to implement buses
A bus line
Enable2
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 43

Complementary Metal Oxide Semiconductor (CMOS)
 Gate output :

Open-drain
 An external pull-up resistor is needed
a
y
b
Pull-up
resistor
Open drain
symbol
Open-drain outputs are often used
To drive displays and lights
To implement buses
+5 v
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 44

Complementary Metal Oxide Semiconductor (CMOS)
 Gate output :

Open-drain
 Gate outputs can be short circuited
A bus line
+5 v
You can short
circuit open-drain
gate outputs
+5 v
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Technology of components/chips
 Transistor-Transistor Logic (TTL)


Uses bipolar transistors
Consists of two sets of families
 Commercial : 74xxxx
•
•
Cheaper
Widely available
 Military : 54xxxx
•
•
Manufactured for more stringent applications
Expensive
Silicon
Silicon Germanium
(SiGe)
Unipolar
CMOS
Gallium
Arsenide
Niobium
(Superconducting)
(Not a semiconductor)
Transistor
type
Bipolar
BiCMOS
SSI MSI LSI VLSI ULSI LSI VLSI ULSI
TTL
Substance
used
Transistor
circuit
ECL
SSI MSI LSI
SSI MSI LSI SSI MSI LSI
faster
CS 2204 Spring 2014 Experiment 1 Lab 4
Number of
gates on
the chip
Page 46

Transistor-Transistor Logic (TTL)
 Low density commercial TTL families, each
with a different combination of speed, power,
cost,..
74 (Standard)
 74L (Low-power)
 74S (Schottky)
We will use it
 74LS (Low-power Schottky)
from time to time
 74H (High speed)
 74AS (Advanced Schottky)
 74ALS (Advanced Low-power Schottky)
 74F (Fast)

CS 2204 Spring 2014 Experiment 1 Lab 4
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Transistor-Transistor Logic (TTL)

Unused gate input

1) It can be left unconnected (floating)
a
b
y
Implemented by
an available 3input AND gate
a
b
y
It can be confusing
If the designer leaves the company and a new engineer works on
the circuit it can be confusing especially if the documentation is
not good !
NAND
NAND gate
TTL 2-input NAND gate ON Semiconductor LS TTL Data Manual
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 48

Transistor-Transistor Logic (TTL)

Unused gate input
2) It can be tied to a used input
a
b
y
An available 3-input AND
gate used to implement a
2-input AND gate
 The fan-out of the b signal can be exceeded
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 49
Transistor-Transistor Logic (TTL)


Unused gate input
3) It can be connected to 1 or 0 depending on the gate type,
via a pull-up resistor or pull-down resistor
a
a
b
b
y
y
Pull-down
resistor
Pull-up
resistor
+5 v
0v
CS 2204 Spring 2014 Experiment 1 Lab 4
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
Transistor-Transistor Logic (TTL)
 Gate outputs

Totem-pole outputs
2-input NAND gate implementation
From ON Semiconductor LS TTL
Data Manual
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 51

Transistor-Transistor Logic (TTL)
 Gate outputs

Tri-state outputs
 The output has three values !
• 1, 0 and Hi-Z ≡ High-impedance ≡ Floating ≡ Static voltage
• There is an extra control input, Enable, to enable/disable output
► If disabled, the output value is Hi-Z (high-impedance)
a
y
b
Enable
Enable
y
0
Hi-Z
1
ab
Operation table
Tri-state symbol
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 52

Transistor-Transistor Logic (TTL)
 Gate outputs

Tri-state outputs
 A tri-state gate can be envisioned as a totem-pole gate with a
switch at the output
y
a
Output y has
three values
a
y
b
b
Enable
Totem-pole gate
Enable
0
Switch
closed
Switch
open
1
CS 2204 Spring 2014 Experiment 1 Lab 4
Hi-Z
Page 53

Transistor-Transistor Logic (TTL)
 Gate output

Tri-state outputs
 Outputs can be short circuited if only one gate is enabled at a time
Enable1
You can short circuit
tri-state gate outputs
Tri-state outputs are often
used to implement buses
A bus line
Enable2
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 54

Transistor-Transistor Logic (TTL)
 Gate output

Open-collector
 An external pull-up resistor is needed
a
y
b
Pull-up
resistor
Open collector
symbol
Open-collector outputs are often used
To drive displays and lights
To implement buses
+5 v
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 55

Transistor-Transistor Logic (TTL)
 Gate output

Open-collector
 Gate outputs can be short circuited
A bus line
You can short circuit
open-collector gate
outputs
Open-collector outputs
can be short circuited to
implement buses
+5 v
+5 v
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 56

Analysis of the Term Project
 The term project black-box view
 The term project operation diagram
 The term project black box partitioning
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 57

The Analysis of the Term Project
 Polytechnic Playing Machine, Ppm

The term project is human vs. machine
 There are two other Ppm versions which are not term
projects


Machine vs. machine
Human vs. human
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 58

The Term Project, Ppm
 The black-box view
From the input devices
13
19
Ppm
To the output devices
Figure 1. The Ppm black box view.

Ppm is sequential (not combinational)
 A large number of FFs are used !
 We need to partition the Ppm based on major operations
• We have to obtain the operation diagram
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 59
The Term Project, Ppm
 The black-box view

From page 3 of the Term Project Handout
SW7 - SW4 P1SEL
RD0
RD1
4
LD7 - LD4
RD2
RD3
3
SW3 - SW1 TRD
LD3
Add
STR0
STR1
SW0 P1add
LD2 - LD0
STR2
BTN3 P1play
BTN2 P2play
Ppm

CG
CF
CE
CD
CC
BTN1 Reset
CB
Four 7-Segment Displays
CA
A4
BTN0 Shpts
A3
CLK1 Clock
A1
A0
Figure 3. Inputs and outputs of the Ppm term project.
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 60

The term project, Ppm
 The input/output devices of the Ppm (without clock)

From page 2 of the Term Project Handout
All zero when the
FPGA is downloaded/reset
LED Lights
P1SEL
SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0
Position Displays
A display blinks fast if display overflow
All displays blink if points limit exceeded
STR
Random Digit
LD7
PD3 PD2 PD1 PD0
Add
RD
Switches
7-segment displays
Use SW3-SW0 as RD
P1add
LD6
LD5
BTN3
P1play/
NextRDs/
Code digits
LD4
LD3
LD2
LD1
LD0
BTN2
BTN1
BTN0
P2play
Reset
Shpts/
Code digits
Push buttons
Figure 2. FPGABoard Input/Output device utilization of the Ppm Term Project.
Please be gentle with push buttons and switches
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 61

Ppm Simplified Operation Diagram
Reset mode
Press BTN3 4 times
Player 1 mode
Press BTN3
after playing
RD with an
adjacency
Press BTN2 to skip
Press BTN2 after playing
RD without an adjacency
Player 2 mode
Press BTN2
after playing
RD with an
adjacency
Convert the simplified
operation diagram
to a (detailed)
operation diagram
Convert each circle to
one or more circles
(steps or states)
Press BTN3 after
playing RD without
an adjacency
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 62
Reset mode
(Initial state)
Player 1 presses BTN3, P1play, four times to play
Player 1 turns on SW0 if wanted. Player 1 turns on and off one
of SW7-SW4 to select a position. Player 1 turns off SW0 if on
2
Player 1 points being calculated !
3
If one of SW7-SW4 is on
in state 3, a random digit
is input for the machine
player from SW3-SW0
when BTN2 is pressed
Player 1 examines the s ituation !
Player 1 presses BTN3, P1play,
Player 1 presses BTN2, P2play,
to allow the machine player to play
to allow herself to play again if
there is an adjacency
4
Player 2 thinks !
r2
Playe
skips p
lay
Player 2 plays on a pos ition
5
Player 2 points being calculated !
6
Player 1 examines the situation !
Player 1 can press BTN3, Reset, in any
state to return to the Reset state, State 0
Player 1 presses BTN3, P1play,
to allow hers elf to play
Player 1 can press BTN4, Shpts, in any state to see players’ points
la y
pr esse s
P laye r 1 pla y, to skip p
P2
,
2
N
BT
From page 8 of the Term Project Handout
Player 1 can press BTN3, P1play,
in state 1 or 3 to see next two RDs
Player 1 press es BTN2, P2play,
to allow the machine player to
play again if there is an adjacency
Ppm
operation
diagram
The game is reset : 0 points for players, 0s on position displays !
Player 1 thinks !
Player 1 mode
(Player 1 plays)
Ppm
Input/output
relationship
0
1
Player 2 mode
(Player 2 plays)
LD0-LD2 on the
FPGA board
show the
current state
Download to the FPGA chip
Figure 5. The operation diagram of Ppm.
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 63
Reset mode
(Initial state)
Download to the FPGA chip
The game is reset : 0 points for players, 0s on position displays !
Player 1 presses BTN3, P1play, four times to play
1
Points Calculation block
Input/Output Block
Player 1 thinks !
Player 1 mode
(Player 1 plays)
Human play block
Player 1 can press BTN3, P1play,
in state 1 or 3 to see next two RDs
pr esse s
la y
P laye r 1 pla y, to skip p
P2
,
2
N
BT
Player 1 turns on SW0 if wanted. Player 1 turns on and off one
of SW7-SW4 to select a position. Player 1 turns off SW0 if on
2
Player 1 points being calculated !
3
If one of SW7-SW4 is on
in state 3, a random digit
is input for the machine
player from SW3-SW0
when BTN2 is pressed
Player 1 examines the s ituation !
Play check block
Player 1 presses BTN3, P1play,
Player 1 presses BTN2, P2play,
to allow the machine player to play
to allow herself to play again if
there is an adjacency
4
r2
Playe
skips p
lay
Player 2 plays on a pos ition
5
Player 2 points being calculated !
6
Player 1 examines the situation !
Player 1 can press BTN3, Reset, in any
state to return to the Reset state, State 0
Player 1 presses BTN3, P1play,
to allow hers elf to play
Player 1 press es BTN2, P2play,
to allow the machine player to
play again if there is an adjacency
Input/Output
Block is active
in every state
Player 2 thinks !
Player 2 mode
(Player 2 plays)
Machine Play
Block is also
active states
2 and 5
Player 1 can press BTN4, Shpts, in any state to see players’ points
Machine play block
0
Figure 5. The operation diagram of Ppm.
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 64

The Ppm Term Project Partitioning
 We have observed the following major operations






Interfacing to the input/output devices
Handling human player’s play
Controlling display operations based on game rules
Calculating new player points
Determining the machine player play
Hint for general partitioning
 If you cannot figure out major operations, partition
one major operation at a time
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 65
The Ppm Term Project Partitioning
 Any other major operation ?
Control (time) the operations
A Digital System
 All other operations
Reset mode
(Initial state)
Download to the FPGA chip
0
The game is reset : 0 points for players, 0s on position displays !
Player 1 can press BTN3, P1play,
in state 1 or 3 to see next two RDs
Player 1 presses BTN3, P1play, four times to play
Player 1 thinks !
pr esse s
la y
P laye r 1 pla y, to skip p
, P2
BTN 2
Player 1 turns on SW0 if wanted. Player 1 turns on and off one
of SW7-SW4 to select a position. Player 1 turns off SW0 if on
2
Player 1 points being calculated !
3
If one of SW7-SW4 is on
in state 3, a random digit
is input for the machine
player from SW3-SW0
when BTN2 is pressed
Player 1 examines the s ituation !
Player 1 presses BTN3, P1play,
Player 1 presses BTN2, P2play,
to allow the machine player to play
to allow herself to play again if
there is an adjacency
4
Player 2 plays on a pos ition
5
Player 2 points being calculated !
6
Player 1 examines the situation !
Player 1 can press BTN3, Reset, in any
state to return to the Reset state, State 0
Player 1 presses BTN3, P1play,
to allow hers elf to play
Player 1 press es BTN2, P2play,
to allow the machine player to
play again if there is an adjacency
Player 2 thinks !
play
r 2 skips
Playe
Player 1 can press BTN4, Shpts, in any state to see players’ points
1
Player 1 mode
(Player 1 plays)

Player 2 mode
(Player 2 plays)

Figure 5. The operation diagram of Ppm.
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 66

Digital Systems
 A digital system consists of digital circuits

A digital system performs microoperations
 A microprocessor is a digital system
 An iPhone is a digital system
 A computer is a collection of digital systems
MIPS R10000 die
Intel Tukwila die
Sun Niagara die
IBM Power 6 die
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 67

The Ppm Term Project
 Ppm is a digital system !
From the input devices
19
13
Ppm
To the output devices
Figure 1. The Ppm black box view.
 The Ppm term project partitioning

First partitioning of the digital system
 Control Unit
 Data Unit

core
Second partitioning (Data Unit partitioning)





Interfacing to the input/output devices core
Handling human player’s play core
Controlling display operations based on game rules core
Calculating new player points core
Determining the machine player play non-core
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 68

The Ppm Digital System Partitioning
From page 9 of the Term Project Handout
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 69

The term project black box partitioning
• Six schematics for six blocks
•
•
Block 1 : Control Unit
Block 2 : Input/Output
• Experiment 1 is on a circuit in this block
•
•
•
•
Block 3 : Human Play
Block 4 : Play Check
Block 5 : Points Calculation file
Block 6 : Machine
• The Machine Play Block uses all other blocks except the
Human Play Block
• These six schematics are in the ppm.sch file
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 70

Human Play Block, Block 3
 Has 5 inputs and 2 outputs
 Has only combinational circuits to

Indicates that human player has played
 P1played

Indicates that the human player has skipped
 P1skip
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 71

The Ppm Data Unit
 Block 3, Human Play Block
5
Block 3
2
 Very simple for this version of the term project


Makes sure the human player does not play on two or more
positions
Generates P1played and P1skip signals
 It is kept there so that in the future this block can
be used to have another machine player so that it
becomes machine vs. machine
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 72

The Ppm Data Unit
Player 1
has
played
 Block 3, Human Play Block
P1SEL
4
Human Play Block
Block 3
P1played
P1skip
P2playsynch
Core
Figure 12. The detailed view of the input and output signals of the Human Play Block.
From page 21 of the Term Project Handout
5
Block 3
CS 2204 Spring 2014 Experiment 1 Lab 4
Player 1
has
skipped
2
Page 73

The Ppm Data Unit
 Block 3, Human Play Block
The circuit that generates
the P1played signal
P1played is 1 if only
one position is played
by the human player
The circuit that
generates the
P1skip signal
The MUX circuit
implements a
combinational
circuit as will be
discussed in class
The circuit
ensures only one
position is played
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 74

The Ppm Data Unit
 Block 3, Human Play Block
The buffer
is used to
rename the
input
8-to-1 MUX
P1played
Buffer
The MUX
implements a
combinational
circuit
P1skip
A buffer does not implement any logic operation. It
transfers the input to the output. More on it next week
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 75

Assignment by next lab
 Make sure that you have completed Experiment 1

Your experiment will be collected and graded
 The last day to submit Experiment 1 as a team is Friday, March
7, 2014
• We will also collect Experiment 2, by Friday, March 7, 2014
 It will be graded and returned by the following lab
Submit your Experiment 1 during a lab session !
Not during Open Lab Hours !
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 76

Digital Design Conventions
 Digital Circuit Drawing Conventions

Project Information is placed in the lower right
corner
 Company name, and address
 Project name,
 Project dates, etc.
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 77

Digital Design Conventions
 Digital Circuit Drawing Conventions
 CS2204 Related
 Part 1 of Term Project Design Checks
• The team info on the lower right corner is
► In the Name area enter the name of the student who designed
the schematic + the names of the other members of the team
► In the Title area enter “
CS 2204 – Your Lab Section –
Spring 2014”
 Place some space before “CS 2204” so that it is not
right next to the name of the block
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 78

Digital Design Conventions
 Digital Circuit Drawing Conventions

Part 2 of Term Project Design Checks
 Remember to beautify the circuit before submitting it
• Place components of a (sub)block next to each other
and separate (sub)blocks from each other
• Components form horizontal and vertical lines
• Only horizontal and vertical wires drawn
• No need to draw long wires
► One can draw short wires and name them
• No unnecessary wire turns
• No Unnecessary line tanglings
• Wires are not drawn over components, buffers, pads
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 79

Digital Design Conventions
 Logic Circuit Design Conventions

Part 3 of Term Project Design Checks
 If a component has multiple outputs, make sure you use
the needed ones
• If an output is not needed, leave it unconnected
 Outputs should not be short-circuited unless they are
tri-state
• But, we will not use tri-state outputs this semester !
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 80

Digital Design Conventions
 Logic Circuit Design Conventions

Part 4 of Term Project Design Checks
 Make sure the experiment folder name is correct
 Last experiment folder is used for the current
experiment ?
• The termproject folder is used as the experiment
folder ?
 More than 6 schematics are used ?
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 81

Digital Design Conventions
 Logic Circuit Design Conventions

Part 5 of Term Project Design Checks
 Do not forget to save schematics
• Then, do a Xilinx IMPLEMENTATION to have the
changes affect the output
 Read the warnings and errors listed
•
•
Confirm that the warnings are acceptable
The FPGA chip utilization does not have to be 6%
► The utilization depends on the strategy, the intelligence of
the machine player designed
 Perform simulations
• If an output value is Hi-Z during simulation, make
sure it is correct
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 82

Digital Design Conventions
 Digital Circuit Printing Conventions

The printout must be readable
 Labels, component names, symbols, etc.

If the circuit is large, it must be printed on
several pages
 The sheets must be attached to each other
 Lines, labels, etc. must be continuous from one sheet to
the next
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 83

Common Logic Errors
 Discovering logic errors by means of simulations
The correct expression
Must be
corrected
a
Input “a” is input “b”
by mistake !
y(a, b, c) = a.b + a.c
b
b
c
y(a, b, c) = a.b.(b.c)
U3
Must be corrected
The OR gate is an AND gate by mistake !
The incorrect
expression
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 84

Common Logic Errors
 Discovering logic errors by means of simulations
U1
U2
U2 has no Load
Must be
U2 output is not used corrected
a
Must be
corrected
U4 input has no driver
U4 input is not
connected to an output.
Its input value is Hi-Z
(High-Impedance) as
there is infinite
impedance (resistance)
into the U4 input so no
current can flow in
U4
b
y
a
c
U3
Must be corrected
Multiple drivers on output y
U3 and U4 outputs are short circuited
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 85
Make sure you have the LABS account and see the S drive
Make sure you have installed WebPACK 12.4 on your laptop
Make sure you create a CS2204 folder on both
Read slides at the end to learn about the software, Project Manager,
Schematic design and other related topics
Do not leave the lab before your partners finish
► Help your partners
QUESTIONS ?
Continue
reading the
Term
Project
handout
Digital
Logic
and
State Machine Design
Think about
the machine
player
strategy
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 86

Today’s Individual Xilinx Work
 We will continue with the 4-bit 2-to-1 MUX in Block 2. We will
use our knowledge of 2-to-1 MUXes to modify a portion of the
term project to develop a 4-bit 2-to-1 MUX in the Human Play
Block (Block 3)

The 2-to-1 MUX expression is the same as the one obtained in class
 We will obtain its schematic (circuit diagram)
• We will design a 4-bit MUX by using 1-bit MUXes
 We will do a schematic check
 We will test our design on the computer assuming ideal gates
• Do logic simulations
 We will do a Xilinx IMPLEMENTATION of the project
• To create the bit file
 We will test our design on the FPGA board
• We will program the FPGA chip ≡ download the bit file
• We will use switches and a LED light to test our design on the FPGA board
 Help our partners complete today’s project
 We will continue reading the Term Project handout

Also read slides at the end to learn about the software, Project
Manager, Schematic design and other related topics
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 87

1.
2.
3.
4.
5.
6.
7.
Today’s Individual Xilinx Lab Work
(If you did not do it last week) Copy the termproject folder
and paste it as the exp1 folder to experiment with the Ppm
schematics
Start the Xilinx ISE software and open the Ppm project in
the exp1 folder
Open the schematics and analyze the schematics
Make sure the team info is placed on all the schematics !
Study the 4-bit 2-to-1 MUX schematic in the Input/Output
Block in schematic 2 of the term project to refresh your
memory on the MUX
Replace the 4-bit MUX in Block 2 with four 1-bit MUXes in
Block 3 of the term project by using the circuitry shown on
pages 1 and 2 of Handout 3 and Xilinx components
Do a schematic check on the new design
Perform functional simulations on the 4-bit 2-to-1 MUX
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 88

Today’s Individual Xilinx Lab Work
8.
9.
Perform a Xilinx IMPLEMENTATION
Download the Ppm project to the FPGA chip and play the game
and to verify that the schematic works correctly

Program the FPGA chip

Test the Ppm to see if it is working

If it does not work, inspect your circuit in Block 3 and correct the
circuit
•
Play the game on the FPGA board
10.
11.
Help your partners complete today’s project
Submit your exp1 project once everyone completes the
design
12. Continue reading the Term Project handout

Study and play the other two types of the Ppm game to think
more about the our machine player’s strategy


Human vs. human : ppmhvsh
Machine vs. machine : ppmmvsm

Also read slides at the end to learn about the software, Project
Manager, Schematic design and other related topics
•
Think about the playing strategy of the machine player that will be
designed
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 89

Today’s Individual Xilinx Lab Work
1.
(If you did not do this step last week) Copy the
termproject folder in the CS2204 folder on the S
drive and paste it as the exp1 folder to experiment
with the Ppm schematics as explained in the Lab 3
presentation
2. Start the Xilinx ISE software and open the Ppm
project in the exp1 folder

Double click on the Xilinx ISE Design Suite icon on your
desktop :
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 90

Today’s Individual Xilinx Work
2. Start the Xilinx ISE software and open the Ppm project in the
exp1 folder

Xilinx will show a “Tip of the Day” window in the foreground and
the “ISE Project Navigator” window in the background :
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 91

Today’s Individual Xilinx Work
2.
Start the Xilinx ISE software and open the Ppm project in the exp1
folder

The ISE opens the last project you worked on by default



Though this can be changed by changing the Preferences settings
If you did not open any Xilinx project, it will not open any project as you saw on
the previous slide and see below
Click on OK to close the “Tip of the Day” window :
Note that
this window
can be
turned off
by clicking
on this :
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 92

Today’s Individual Xilinx Work
2. Start the Xilinx ISE software and open the Ppm project in the
exp1 folder

After the “Tip of the Day” window is closed you will see the
following :
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 93

Today’s Individual Xilinx Work
2. Start the Xilinx ISE software and open the Ppm project in the
exp1 folder

Click on Open Project... on the “Start” panel on the left to start
opening the term project
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 94

Today’s Individual Xilinx Work
2.
Start the Xilinx ISE software and open the Ppm project in the exp1
folder


The “Open Project”window will pop up asking you to select the project
folder which is termproject
Select the project folder S;\CS2204\exp1 by using typical Windows
operations

You will see the partial content of the exp1 folder where all six folders and the
“Xilinx ISE Project” file are shown :
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 95

Today’s Individual Xilinx Work
2.
Start the Xilinx ISE software and open the Ppm project in the exp1
folder

Double click on “Xilinx ISE Project” :
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 96

Today’s Individual Xilinx Work
2.
Start the Xilinx ISE software and open the Ppm project in the exp1
folder

Xilinx will open the term project in the exp1 folder :
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 97

Today’s Individual Xilinx Work
3.
Open the schematics and analyze the schematics

Double click on ppm (ppm.sc) to view the six schematics
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 98

Today’s Individual Xilinx Work
3. Open the schematics and analyze the schematics

Take a look at the six schematics for the six blocks
of the term project
•
•
•
•
•
•

Block 1 : Control Unit
Block 2 : Input/Output
Block 3 : Human Play
Block 4 : Play Check
Block 5 : Points Calculation
Block 6 : Machine Play
These six schematics are in the ppm.sch file
CS 2204 Spring 2014 Experiment 1 Lab 4
Page 99

Today’s Individual Xilinx Work
3.
Open the schematics and analyze the schematics

Double click on ppm (ppm.sc) to view the six schematics
 Notice that as the schematic file is open the first schematic sheet is shown and
also the left panel changes to the “Options” panel :
First
schematic
sheet
First
schematic
sheet :
Control
Unit
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 100

Today’s Individual Xilinx Work
3.
Open the schematics and analyze the schematics

Click on 2 to the left of the schematic sheet to view the second schematic sheet :
Second
schematic
sheet
Second
schematic
sheet :
Input/Output
Block
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 101

Today’s Individual Xilinx Work
3.
Open the schematics and analyze the schematics

Click on 3 to the left of the schematic sheet to view the third schematic sheet :
Third
schematic
sheet
Third
schematic
sheet :
Human Play
Block
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 102

Today’s Individual Xilinx Work
3.
Open the schematics and analyze the schematics

Click on 4 to the left of the schematic sheet to view the fourth schematic sheet :
Fourth
schematic
sheet
Fourth
schematic
sheet :
Play Check
Block
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 103

Today’s Individual Xilinx Work
3.
Open the schematics and analyze the schematics

Click on 5 to the left of the schematic sheet to view the fifth schematic sheet :
Fifth
schematic
sheet
Fifth
schematic
sheet :
Points
Calculation
Block
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 104

Today’s Individual Xilinx Work
3.
Open the schematics and analyze the schematics

Click on 6 to the left of the schematic sheet to view the sixth schematic sheet :
Sixth
schematic
sheet
Sixth
schematic
sheet :
Machine
Play
Block
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 105

Today’s Individual Xilinx Work
3. Open the schematics and analyze the schematics
 There are six schematics !
We are covering these schematics in detail !
The Term Project handout discusses the schematics in detail !
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 106

Today’s Individual Xilinx Work
3.
Open the schematics and analyze the schematics

Take a look at the six schematics for the six blocks of the
term project
•
Blocks 1, 2, 3, 4 and 5 are core blocks
•
•
All of their circuits are given
Block 6 is completely non-core
•
Students will replace all the circuits with their own circuits
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 107
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Today’s Individual Xilinx Lab Work
3. Open the schematics and analyze the
schematics

Take a look at the six schematics for the six
blocks of the term project
•
Each block (schematic) consists of subblocks and
subsubblocks
• The software identifies each schematic sheet by
automatically assigning it a number
• Subblocks and subsubblocks are identified by their
names and distance and lines between them on the
schematic sheet
• Common document processor editing rules and key
sequences apply to edit schematics
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 108
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Today’s Individual Xilinx Lab Work
3. Open the schematics and analyze the schematics

All components use the same convention that
inputs are on one side and outputs are on the
other side


There are exceptions like 4-bit ADDers, and sequential
circuits (flip-flops, registers, counters, etc.) that
additional inputs are on the remaining two sides as well
Black boxes students will implement (M2 and M3)
use the same convention :


Inputs are one side
Outputs are on the other side
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 109
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Today’s Individual Xilinx Lab Work
3.
Open the schematics and analyze the schematics

Enter team information on the schematics if it is not entered
•
To enter the team info schematic 1 switch to schematic 1 and zoom
into the lower right corner where project information is shown :
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 110
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Today’s Individual Xilinx Lab Work
3.
Open the schematics and analyze the schematics

Enter team information on the schematics if it is not entered
•
To enter the team info on schematic 1 switch to schematic 1 and zoom
into the lower right corner where project information is shown :
•
•
•
Right click on the project information object
Select Object Properties
In the NameFieldText area enter the names of the members of the
team
In the Title area enter “
CS 2204 – Your Lab Section – Spring 2014”
• Place some space before “CS 2204” so that it is not right next to
“Ppm Control Unit”
•
CS 2204 Spring 2014 Experiment 1 Lab 4
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Today’s Individual Xilinx Lab Work
3.
Open the schematics and analyze the schematics

Enter team information on the schematics if it is not entered
•
•
•
•
To enter the team info on schematic 1 switch to schematic 1 and zoom
into the lower right corner where project information is shown
Save the schematic to record the changes
After you save, the Date area is automatically entered the date and
time the save was done
After you enter all the information, the project information area in
schematic 1 will look like as follows for an imaginary team :
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 112
Today’s Individual Xilinx Lab Work

3.
Open the schematics and analyze the schematics

Enter team information on the schematics if it is not entered

The Project Navigator window after the schematic is saved is different
where there are
symbols next to Synthesis, Implement Design and
Generate Programming File steps in the Processes section, signaling that
they must be done to incorporate these changes to the design
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 113
Today’s Individual Xilinx Lab Work

3.
Open the schematics and analyze the schematics

Enter team information on the schematics if it is not entered


Repeat these steps above for the remaining five schematics so that they all
have the same team information
The Project Navigator window will still have
symbols next to Synthesis,
Implement Design and Generate Programming File steps in the Processes
section
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 114
Today’s Individual Xilinx Lab Work

3.
Open the schematics and analyze the schematics

Enter team information on the schematics if it is not entered



Repeat these steps above for the remaining five schematics so that they all
have the same team information
The Project Navigator window will still have
symbols next to Synthesis,
Implement Design and Generate Programming File steps in the Processes
section
In order to record these changes, we have to save the
schematic and do a synthesis
•
•
•
•
Save the schematic
Perform a Synthesis operation by double clicking on the
Synthesize – XST process on the Project Navigator panel
Switch to the Design Summary panel and notice that there are
137 warnings
 We know this due to the fact that we are working on a copied and
pasted project and the ISE is complaining about the paths
Right click and select ReRun on the Synthesize – XST process
on the Project Navigator panel to eliminate the unnecessary
warnings
 The new number of warnings is 63 as it is the case with the term
project and the symbol next to the Synthesize – XST process is
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 115
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Today’s Individual Xilinx Lab Work
4. Study the 4-bit 2-to-1 MUX schematic in the Input/Output
Block in schematic 2 of the term project to refresh your
memory on the MUX
a)
Take a look at the MUX labeled U80

DDISP circuit is a 4-bit 2-to-1 MUX
•
•
Selects between DISP and P2PT
Uses DISPSEL0 as the select signal
DDISP operation table
DISPSEL0
Operation
0
DDSIP = DISP
1
DDISP = P2PT
We need a 4-bit 2-to-1 MUX
Do we design it ?
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 116
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Today’s Individual Xilinx Lab Work
4.
Study the 4-bit 2-to-1 MUX schematic in the Input/Output
Block in schematic 2 (ppm2.sch) of the term project to
refresh your memory on the MUX
a)
Take a look at the MUX labeled U80

DDISP circuit is a 4-bit 2-to-1 MUX
We need a 4-bit 2-to-1 MUX
We do not design it : It
has already implemented &
it is satisfactory for us
u74_157
A
4-bit 2-to-1 MUX
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 117
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Today’s Individual Xilinx Lab Work
4.
Study the 4-bit 2-to-1 MUX schematic in the Input/Output Block in schematic
2 of the term project to refresh your memory on the MUX
a)
Take a look at the MUX labeled U80

What is the G input ?
•
•
The G input is a control input which is the enable input
If the Enable input is 1 all four outputs are 0
•
The G input is active low !
•
The circle (bubble) at the G input indicates it is active low ! simulations on the 4-
bit 2-to-1 MUX in to refresh your memory on the MUX and simulations
The 4-bit 2-to-1
MUX operation table
G
S
Operation
1
X
Y=0
0
0
Y=A
0
1
Y=B
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 118
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Today’s Individual Xilinx Lab Work
4.
Study the 4-bit 2-to-1 MUX schematic in the Input/Output Block in
schematic 2 of the term project to refresh your memory on the MUX
a)
Take a look at the MUX labeled U80
 What is the GND ?
• GND ≡ Ground ≡ 0 Volts ≡ 0
• The G input is permanently connected to 0 !
•
Since the Enable is permanently 0, the outputs are always enabled
How DDISP uses the MUX
G DISPSEL0 Operation
G = 0  Only these two
rows are valid for U80
1
X
DDISP = 0
0
0
DDISP = DISP
0
1
DDISP = P2PT
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 119
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Today’s Individual Xilinx Lab Work
4. Study the 4-bit 2-to-1 MUX schematic in the Input/Output
Block in schematic 2 of the term project to refresh your
memory on the MUX
a)
Take a look at the MUX labeled U80
 Implementing a 4-bit 2-to-1 MUX ?
•
•
•
Based on major operations on the operation table !
Major operations are not explicit on the previous operation table
Obtain a more detailed operation table
The 4-bit 2-to-1 MUX operation table
The 4-bit 2-to-1
MUX operation table
G
S
Operation
G
S
1
0
0
X Y3=0, Y2=0, Y1=0, Y0=0
0 Y3=A3, Y2=A2, Y1=A1, Y0=A0
1 Y3=B3, Y2=B2, Y1=B1, Y0=B0
1
0
0
X
0
1
•
Operation
Y = 0
Y = A
Y = B
There are four identical major operations : 1-bit 2-to-1 MUXing
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 120
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Today’s Individual Xilinx Lab Work
4.
Study the 4-bit 2-to-1 MUX schematic in the Input/Output
Block in schematic 2 of the term project to refresh your
memory on the MUX
a)
Take a look at the MUX labeled U80
 See how the 4-bit 2-to-1 MUX is designed
•
•
•
•
Do a Hierarchy Push to see the implementation of
the 4-bit 2-to-1 MUX by
Right clicking on the MUX and selecting Symbol ->
Push into Symbol
Confirm that it has four 1-bit Xilinx 2-to-1 MUXes
See the implementation of the 4-bit MUX on the
next slide
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 121
Today’s Individual Xilinx Lab Work

4.
Study the 4-bit 2-to-1 MUX schematic in the Input/Output Block in
schematic 2 of the term project to refresh your memory on the
MUX
a)
Take a look at the MUX labeled U80
The 4-bit 2-to-1 MUX operation table
G
S
Operation
1
X
Y3=0, Y2=0, Y1=0, Y0=0
0
0
Y3=A3, Y2=A2, Y1=A1, Y0=A0
0
1
Y3=B3, Y2=B2, Y1=B1, Y0=B0
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 122
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Today’s Individual Xilinx Lab Work
4.
Study the 4-bit 2-to-1 MUX schematic in the Input/Output
Block in schematic 2 of the term project to refresh your
memory on the MUX
a)
Take a look at the MUX labeled U80

Do another Hierarchy Push to see the implementation
of one of the (1-bit) 2-to-1 MUXes and confirm that it
is similar what we discussed in class, except
• The AND gates have three inputs since the enable
input is connected to the AND gates to control the
output
• The separate inverter we have in mux2to1 is
implemented by a special Xilinx AND gate, AND3B1
► One input of the AND gate is internally inverted
•
See the Xilinx implementation of the 1-bit MUX on
the next slide
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 123
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Today’s Individual Xilinx Lab Work
4. Study the 4-bit 2-to-1 MUX schematic in the Input/Output
Block in schematic 2 (ppm2.sch) of the term project to
refresh your memory on the MUX
a)
Take a look at the MUX labeled U80
A Xilinx specific 3-input
AND gate with an input
inverted internally : AND3B1
Xilinx 1-bit 2-to-1
MUX operation table
E
S
Operation
1
X
O = 0
0
0
O = D0
0
1
O = D1
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 124
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Today’s Individual Xilinx Lab Work
4. Study the 4-bit 2-to-1 MUX schematic in
the Input/Output Block in schematic 2 of
the term project to refresh your memory on
the MUX
a)
Take a look at the MUX labeled U80

Close the two schematics by clicking on the Close Tab
buttons on the bottom of the schematic display
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 125

Today’s Individual Xilinx Lab Work
4.
Study the 4-bit 2-to-1 MUX schematic in the Input/Output Block in
schematic 2 of the term project to refresh your memory on the
MUX
b)
Perform functional simulations on the 4-bit 2-to-1 MUX in to
refresh your memory on the MUX and simulations :
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 126
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Today’s Individual Xilinx Lab Work
5.
Replace the 4-bit MUX in Block 2 with four 1-bit MUXes in
Block 3 of the term project by using the circuitry shown on
pages 1 and 2 of Handout 3 and Xilinx components
a)
Delete the 4-bit 2-to-1 MUX in Schematic 2

Switch to schematic 2, if it is not the schematic viewed
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 127
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Today’s Individual Xilinx Lab Work
5.
Replace the 4-bit MUX in Block 2 with four 1-bit
MUXes in Block 3 of the term project by using the
circuitry shown on pages 1 and 2 of Handout 3 and
Xilinx components
a) Delete the 4-bit 2-to-1 MUX in Schematic 2


Select the 4-bit 2-to-1 MUX by clicking on it
Press Delete to delete it
•

Do not delete the wires of the MUX
See modified schematic 2 on the next slide
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 128
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Today’s Individual Xilinx Lab Work
5.
Replace the 4-bit MUX in Block 2 with four 1-bit MUXes in
Block 3 of the term project by using the circuitry shown on
pages 1 and 2 of Handout 3 and Xilinx components
4-bit
2-to-1
MUX
deleted
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 129
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Today’s Individual Xilinx Lab Work
5.
b)
c)
d)
Replace the 4-bit MUX in Block 2 with four 1-bit MUXes in
Block 3 of the term project by using the circuitry shown on
pages 1 and 2 of Handout 3 and Xilinx components
Switch to the Human Play Block, Block 3
Zoom into the upper left side of the schematic
Place a Xilinx 1-bit 2-to-1 MUX, M2_1, in the very upper left
corner of the schematic as shown on page 1 of Handout 3 and on
the next two slides

The wire names are changed
•
•
•
•


Input A is DISPSEL0 (The Xilinx name is S0)
Input B is DISP12 (The Xilinx name is D0)
Input C is P2PT(4) (The Xilinx name is D1)
Output Y is DDISP12 (The Xilinx name is O)
Give label U272 (because the last component label is U271 in Block 6)
to the MUX
See next two slides to visualize this MUX
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 130
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Today’s Individual Xilinx Lab Work
5.
Replace the 4-bit MUX in Block 2 with four 1-bit MUXes in
Block 3 of the term project by using the circuitry shown on
pages 1 and 2 of Handout 3 and Xilinx components
1-bit
2-to-1
MUX
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 131

Today’s Individual Xilinx Lab Work
5.
Replace the 4-bit MUX in Block 2 with four 1-bit MUXes in
Block 3 of the term project by using the circuitry shown on
pages 1 and 2 of Handout 3 and Xilinx components
1-bit
2-to-1
MUX
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 132
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Today’s Individual Xilinx Lab Work
5.
Replace the 4-bit MUX in Block 2 with four 1-bit MUXes in
Block 3 of the term project by using the circuitry shown on
pages 1 and 2 of Handout 3 and Xilinx components
e) Place two more Xilinx 1-bit 2-to-1 MUXes, M2_1, in the
upper left corner of the schematic as shown on page 1 of
Handout 3 and on the next two slides







Copy the circuit just selected
Right click anywhere on the screen select Paste Special…
When the “Paste Special” window is shown select Use new
name for all nets and then click OK
Place the copied Xilinx MUX to the right side of the (1-bit) 2-to-1
MUX just designed
• Rename the inputs and outputs as DISP13, P2PT(5), DISPSEL0
and DDISP13, respectively
Repeat the above steps to place one more Xilinx MUX to place it
below the first (1-bit) 2-to-1 MUX designed
• Rename the inputs and outputs as DISP14, P2PT(6), DISPSEL0
and DDISP14, respectively
Give labels U273 and U274 to the MUXes just placed
See next two slides to visualize these MUXes
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 133
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Today’s Individual Xilinx Lab Work
5.
Replace the 4-bit MUX in Block 2 with four 1-bit MUXes in
Block 3 of the term project by using the circuitry shown on
pages 1 and 2 of Handout 3 and Xilinx components
e) Place two more Xilinx 1-bit 2-to-1 MUXes
Three
1-bit
2-to-1
MUXes
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 134
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Today’s Individual Xilinx Lab Work
5.
Replace the 4-bit MUX in Block 2 with four 1-bit MUXes in
Block 3 of the term project by using the circuitry shown on
pages 1 and 2 of Handout 3 and Xilinx components
The new
1-bit
2-to-1
MUXes
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 135

Today’s Individual Xilinx Lab Work
5.
Replace the 4-bit MUX in Block 2 with four 1-bit MUXes in
Block 3 of the term project by using the circuitry shown on
pages 1 and 2 of Handout 3 and Xilinx components
f) Place the last MUX as a gate network




Draw the gate network, a 1-bit 2-to-1 MUX as explained in
the classroom with the following exceptions
The wire names are changed
•
•
•
•
•
Input A is DISPSEL0
Input B is DISP15
Input C is P2PT(7)
Output Y is DDISP15
The output of the NOT gate is labeled NotDISPSEL0
•
•
•
The NOT gate is labeled U275
The AND gates are labeled U276 and U277
The OR gate is labeled U278
Label the gates starting at U275
See next two slides to visualize this MUX
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 136
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Today’s Individual Xilinx Lab Work
5.
f)
Replace the 4-bit MUX in Block 2 with four 1-bit MUXes in
Block 3 of the term project by using the circuitry shown on
pages 1 and 2 of Handout 3 and Xilinx components
Place the last MUX as a gate network
4-bit
2-to-1
MUX
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 137

Today’s Individual Xilinx Lab Work
5.
Replace the 4-bit MUX in Block 2 with four 1-bit MUXes in
Block 3 of the term project by using the circuitry shown on
pages 1 and 2 of Handout 3 and Xilinx components
1-bit
2-to-1
MUX
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 138

Today’s Individual Xilinx Lab Work
5.
Replace the 4-bit MUX in Block 2 with four 1-bit MUXes in
Block 3 of the term project by using the circuitry shown on
pages 1 and 2 of Handout 3 and Xilinx components
f) Place the last MUX as a gate network

Make sure that you
• Appropriately name the new wires
• Appropriately label the new gates
The last component label is U278



Make sure your circuit is beautified so that it is easier to
follow the schematic
Save the schematic
See modified Block 3 on the next slide
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 139

5.
Today’s Individual Xilinx Lab Work
Replace the 4-bit MUX in Block 2 with four 1-bit MUXes in Block 3 of the
term project by using the circuitry shown on pages 1 and 2 of Handout 3
and Xilinx components
4-bit
2-to-1
MUX
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 140

5.
Today’s Individual Xilinx Lab Work
Replace the 4-bit MUX in Block 2 with four 1-bit MUXes in Block 3 of the
term project by using the circuitry shown on pages 1 and 2 of Handout 3
and Xilinx components

The Project Navigator window will still have
symbols next to Synthesis,
Implement Design and Generate Programming File steps in the Processes
section
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 141

Today’s Individual Xilinx Lab Work
6. Do a schematic check on the new design
 The schematic check is to see if there
are simple errors to catch on all
schematics

Select Tools  Check Schematic
• The Console panel will indicate that there
are no errors but two warnings
 See the next slide
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 142
Today’s Individual Xilinx Lab Work

6.
Do a schematic check on the new design
The console panel has the following message


The warnings are about
•
•
An unused (unconnected) output in Block 4
The unused wire attached to GND in Block 2 where GND was supplying the
Enable input to the deleted MUX
The two warnings are OK since we do not need these outputs
We will ignore these unneeded output warnings and decide there is
nothing to correct
You might wonder how the project works if wires are not connected to
outputs nor inputs






The Xilinx software integrates all the schematics during its implementation
If the wire names are the same, it would not matter where the wires is placed,
the software connects them internally
See the next slide
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 143

Today’s Individual Xilinx Lab Work
6.
Do a schematic check on the new design
 The schematic check is to see if there are simple errors
to catch on all schematics
 Read the bottom portion of the Console panel for warnings and
correct them if there are any
•
•
The warnings are about unused (unconnected) outputs which are
correct since we do not need these outputs
We will ignore these unneeded output warnings and decide there
is nothing to correct
 You might wonder how the project works if wires are not
connected to outputs nor inputs
•
•
The Xilinx software integrates all the schematics during its
implementation
If the wire names are the same, it would not matter where the
wires is placed, the software connects them internally
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 144

7.
Today’s Individual Xilinx Lab Work
Perform functional simulations on the 4-bit 2-to-1 MUX
Since we changed the schematics to reimplement the MUX we have to
do a synthesis to record the changes

Click on Design Summary (out of date) to be able to see number of errors
and warnings
Double click on Synthesize – XST
Wait until you read the following line on the Console panel :



Process "Synthesize - XST" completed successfully
Check the number of errors and warnings on the upper right side of the
Design Summary panel

•
•
•
There should be 0 errors and 64 warnings
There is a new warning since a wire that connected GND and the MUX G input is
not connected anywhere
The software message on the warning is as follows :
Xst:646 - Signal <XLXN_88> is assigned but never used.
This unconnected signal will be trimmed during the
optimization process.
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 145

7.
Today’s Individual Xilinx Lab Work
Perform functional simulations on the 4-bit 2-to-1 MUX
Since we changed the schematics to reimplement the MUX we have to
do a synthesis to record the changes

Check the number of errors and warnings on the upper right side of the
Design Summary panel

•
•
•
In Digital Logic
terminology,
a net is a wire
One can search for wires on the schematic as follows

•
•
•
•
•
•
•
•

There should be 0 errors and 64 warnings
There is a new warning since a wire that connected GND and the MUX G input is
not connected anywhere
We can search for this wire to confirm that it is actually that wire
Press Ctrl-F or Click Edit -> Find…
When the Find window pops up select Nets on What
Enter XLXN_88 in the Net Name area
Click Find
The software will automatically switch to Block 2 and show the wire in yellow
It is indeed the wire that connected GND to the deleted MUX
We can ignore this wire
Close the window
Since we did the synthesis, we can do simulations !
Xst:646 - Signal <XLXN_88> is assigned but never used.
This unconnected signal will be trimmed during the
optimization process.
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 146

7.
Today’s Individual Xilinx Lab Work
Perform functional simulations on the 4-bit 2-to-1 MUX

The Simulation window when it simulates the 4-bit 2-to-1 MUX
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 147

Today’s Individual Xilinx Lab Work
8.
Perform a Xilinx IMPLEMENTATION
•
Xilinx IMPLEMENTATION is required after a schematic
is changed
•
•
•
When we indicate IMPLEMENTATION we mean Synthesis,
Implement Design and Generate Programming File steps we
see on the Project Navigator window
Since we changed all the schematics to enter the team info
and/or to work on the MUX, we have to do a Xilinx
IMPLEMENTATION
Xilinx IMPLEMENTATIONS are needed for three reasons



Catching more errors not discovered via schematic checks
and functional simulations as the software analyzes the
schematics
Catching even more errors by doing timing simulations
possible after the Xilinx IMPLEMENTATION
Creating a new bit file
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 148

Today’s Individual Xilinx Lab Work
8.
Perform a Xilinx IMPLEMENTATION
•
Xilinx IMPLEMENTATION maps the schematics to the
FPGA resources (CLBs and wires)

•
If the mapping is complete then there are no errors but
there can be warnings
• Mapping allows real components to be considered, hence
timing simulations
Xilinx IMPLEMENTATION consists of 3 major steps
•
•

Synthesis to translate the schematic to a netlist file after
converting the schematic to a VHDL file
Implement Design which consists of
• Translate, Map, Place & Route
Generate Programming File to generate the bit file
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 149

Today’s Individual Xilinx Lab Work
8. Perform a Xilinx IMPLEMENTATION


Click on Design Summary (out of date) to be able to see number
of errors and warnings
Right click on Generate Programming File and select Rerun All


We will do the Synthesis, Implement Design and Generate Programming File
steps altogether
•
Even though we already did the synthesis, we will do it again to get
practice on this as we will do it many times
•
The question mark next to ppm1.sch is changed to a check mark
Wait until the IMPLEMENTATION completes
•
If it does not complete, it stops at one of the steps
 We have to read the errors to read on the Design Summary panel


Once completed, there are no marks next to any one of the steps
just performed
See the Project Navigator window on the next slide
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 150
Today’s Individual Xilinx Lab Work

8.
Perform a Xilinx IMPLEMENTATION

The Project Navigatorwindow looks like this after the
IMPLEMENTATION is completed successfully :
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 151

Today’s Individual Xilinx Lab Work
8. Perform a Xilinx IMPLEMENTATION

For the current IMPLEMENTATION we will get

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0 Errors
66 Warnings one higher than the termproject project due to
the wire unused in Block 2 : XLXN_88
6% Slice utilization
Read the warnings by clicking on 66 Warnings on the
Design Summary window whether or not the Xilinx
IMPLEMENTATION completes
We often check Design Summar yfor the warnings and the
FPGA utilization
•
•

Most warnings we check are in the Synthesis section
The FPGA utilization is lower than expected if there are
errors or warnings that must be corrected
In Experiment 1, the number of warnings will be 66

This number will change depending on the experiment
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 152
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Today’s Individual Xilinx Lab Work
8.
Perform a Xilinx IMPLEMENTATION

The IMPLEMENTATION warnings

Why do we have 66 not 65 ?
• The termproject had only 65 warnings !
• There is a new warning !
• It is because a wire in Block 2 is not used
Xst:646 - Signal <XLXN_88> is assigned but never used. This
unconnected signal will be trimmed during the optimization process.

This wire is the wire that connected the “G” input of the
Xilinx MUX to the GND in Block 2
This warning is OK
We will ignore it
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 153

Today’s Individual Xilinx Lab Work
8.
Perform a Xilinx IMPLEMENTATION

The IMPLEMENTATION warnings

How can I search for this wire in the schematics ?
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•
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Press Ctrl-F or Click Edit -> Find…
When the Find window pops up select Nets on What
Enter XLXN_88 in the Net Name area
Click Find
The software will automatically switch to Block 2 and show the
wire in yellow
It is indeed the wire that connected GND to the deleted MUX
We can ignore this wire
Close the window
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 154
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Today’s Individual Xilinx Lab Work
8. Perform a Xilinx IMPLEMENTATION

The FPGA utilization
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The term project now has 6% slice utilization :
Number of occupied Slices: 282 out of 4656 6%
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 155

9.
Today’s Individual Xilinx Lab Work
Download the Ppm project to the FPGA chip and
play the game and to verify that the schematic
works correctly
Program the FPGA chip
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Test the Ppm to see if it is working
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The developed 4-bit MUX handles the leftmost display
•
Play the game on the FPGA board
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Compare your design with the Term Project Check List handout
to see if your design follows the handout
If yes, copy your Experiment 1 folder from the S drive and to
your laptop
 If push button BTN4 is not pressed, it shows the position displays,
i.e. the random digit plays
 If push button BTN4 is pressed, it shows the leftmost Hex digit of
Player 2 points
If it does not work, inspect your circuit in Block 3 and
correct the circuit
If you are sure your circuit is correct then
•
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 156
Today’s Individual Xilinx Lab Work

10.
Help your partners complete today’s project
11.
Submit your exp1 project once everyone
completes the design
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If all the team members have finished the 4-bit MUX
design (Step 9 on the previous slide), they will decide
whose project will be submitted
Students will fill out a Term Project Check List handout
so that feedback can be given to them by the grading
TAs
Students will signal to a TA who will copy their project
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 157
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Today’s Individual Xilinx Lab Work
12.
Continue Reading the Term Project handout
Study and play the other two types of the Ppm game to
think more about the our machine player’s strategy
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

Human vs. human : ppmhvsh
Machine vs. machine : ppmmvsm
•
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Think about the playing strategy of the machine player that will
be designed
Make sure you refresh your memory about the game rules
and how to play the game
Also read slides at the end to learn about the software,
Project Manager, Schematic design and other related topics
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 158

Understand Critical Wires
RD : 4 bits
 The random digit
R1D : 4 bits
Next random digit
R2D : 4 bits
The random digit after next random digit
DISP : 16 bits
 They represent the four position displays
 In Hex
 DISP15-DISP12 : The leftmost position display, PD3
 DISP11-DISP8 : position display PD2, etc
NPDISP : 16 bits
 The result of RD to each display digit
 In Hex
 NPDISP15-NPDISP12 : The leftmost position, PD3, value + RD
 NPDISP11-NPDISP8 : Position display PD2 value + RD
NPSELDISP : 4 bits
 Selects one of NPDISP display values
 In Hex
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 159

Understand Critical Wires
BRWD : 4 bits
 Basic reward
 In Hex
 The digit played and also minimum points earned
 It is selected from RD or NPSELDISP
 Based on how the player played : Directly or with an addition
Brwdeqz : 1 bit
 BRWD is zero when it is 1
PDPRD : 4 bits
 Display overflow bits after addition
Pdprd : 1 bit
The display overflow bit of the position played
Selplyr : 1 bit
 The current player
 If it is 0, it is the human player, otherwise, it is the machine
player
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 160

Understand Critical Wires
P1SEL : 4 bits
 The position played by the human player
P2SEL : 4 bits
 The position played by the machine player
PSEL : 4 bits
 Position Select bits of current player
ENCPSEL : 2 bits
 The number of the position played
EQ : 4 bits
 The equality of the four displays to the digit played
NSD : 2 bits
 The number of similar digits, i.e. the adjacency information of the
position played
RWD : 8 bits
 The regular reward points calculated based on adjacencies
 In Unsigned Binary
CODERWD : 8 bits
 The code reward points calculated based on the code digits
 In Unsigned Binary
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 161

Understand Critical Wires
P1PT : 8 bits
 Player 1 points
 In Hex
P2PT : 8 bits
 Player 2 points
 In Hex
PT : 8 bits
 The points of the current player
 In Hex
NPT : 8 bits
 New player points for the current player
 In Hex
Ptovf : 1 bit
The points overflow
 if it is 1, the new player points is above (255)10
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 162

Understand Critical Wires
P1add : 1 bit
 Player 1 adds when it is 1
P2add : 1 bit
 Player 2 adds when it is 1
Add : 1 bit
 The current player adds when it is 1
P1skip : 1 bit
 Player 1 skips when it is 1
P2skip : 1 bit
 Player 2 skips when it is 1
P1played : 1 bit
 Player 1 has played when it is 1
P2played : 1 bit
 Player 2 has played when it is 1
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 163

Understand Critical Wires
DISPSEL : 2 bit
 Selects one of four values for displays
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00 Selects position displays (displays that RD is played on)
01 Selects player points
10 Selects next two random digits
11 Selects discovered code digits
Add : 1 bit
Shows that the current player has selected to add
Stp1pt : 1 bit
 Store Player 1 points
Stp2pt : 1 bit
 Store Player 2 points
Grd : 1 bit
 Signals to generate a new random digit
 The random digit counter output is stored as P2RD while P2RD and
P1RD are shifted to generate the new P1RD and RD
Bpds : 1 bit
Blink one or all displays slowly
Bpdf : 1 bit
Blocks a display fast after a display overflow
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 164

Understand Critical Wires
Clear : 1 bit
 Clear FFs, registers, counters, etc. during reset in Block 2, Block 4
and Block 6 so that it can play again
Clearp2ffs : 1 bit
 Clears Player 2 FFs, counters and registers
Clff : 1 bit
 Clears FFs in Block 2 so that the next player can play if there is no
overflow
S1 : 1 bit
 State 1 where when it is 1, the Ppm is in state 1
P2sturn : 1 bit
 Signals that Player 2 has the turn
 It is 1 when the Ppm is in state 4
Sysclk : 1 bit
 System clock of the operation diagram at 6 Hz
 P2clk : 1 bit
 The clock signal of Player 2 at 48 Hz
 Rdclk : 1 bit

The random digit counter clock at 192 Hz
CS 2204 Spring 2014 Experiment 1 Lab 4 Page 165