Transcript Presentation Title – Title Caps – 24 Pt Font Subtitle Goes

Paradigm Shift to 3D and its Impact
on our EcoSystem, Standards and EDA Tools
Herb Reiter, eda2asic Consulting
Chairman of GSA EDA Interest Group
& 3D IC Working Group
EDPS, Monterrey, April 8, 2011
Agenda
 “2D ICs” make continued innovation very expensive

Need EcoSystem changes to enable many of us to continue innovating
 3D demands closer cooperation AND additional standards

Data exchange formats & tools interoperability foster cooperation

Complex assembly processes and much higher packing densities
demand more rules (… like living in a condo complex vs on a 50 ac ranch…)
 3D technology offers new opportunities for EDA

3D is a SYSTEM integration technology, not limited to IC design

Opens up a wide range of EDA opportunities:
- Engage in multi-level modeling
- Make proven 2D tools “3D aware”
- Solve complex system-level H/W & S/W planning, implementation
& verification challenges with EDA tools, flows and methodologies
- DFT for economical testing of 3D ICs
 Discussion, conclusions, action items
Challenges with the proven 2D SoCs
• 2+ years development time
• Software is ~ ½ of the TTM
• NREs of $ 100M and more
demand very high volumes
to reach breakeven point
• RISKs: Design error
Market changes
Competitor moves 1st
Synopsys Keynote, @ LSI, Oct 6, 2010
Major Implementation Alternatives
Source: eda2asic article in Yole’s 3D Packaging Magazine, Nov 17, 2010
2½ + 3D Commercialization Schedules
2½D with
= this year
Dr. Phil Garrou, YOLE http://www.i-micronews.com/lectureArticle.asp?id=6351
Semiconductor EcoSystem
 Characteristics of our current EcoSystem




ICs, packages and PCBs are designed (almost) in isolation
Monolithic “2D ICs” are hitting economical and technical limits
Several modular solutions (PoP, PiP, SiP,… ) are production proven
New 2½D* and 3D configurations are emerging as alternatives
to integrate ICs and entire systems (*: 2½D = interposer-based)
 What do most of our end customers want ?
 Lower cost, smarter, faster, smaller systems with longer battery life
 Following latest trends quickly ( shorter time-to-market in design & manuf.)
 How can we meet these requirements ?
 Architect for 3D implementations (utilize wide I/O, A & D, MEMS, passives)
- Higher level of integration allows reduced power and increased speed
- Lots of memory & S/W to increase user friendliness and update systems
- IP reuse and modularity to reduce development time and –cost
 Add’l standards to simplify cooperation & drive economies of scale
 Investments in our design- and manufacturing EcoSystem
Cooperation Within the “Food-Chain”
Fabless/light vendor: Idea, architecture, targets for COST, Power, Performance, FormFactor, …
Complete Product
Software Partner: OS
H/W & S/W Appl. S/W
co-design needs, Drivers
memory footprint,
performance,
power dissipation, …
Foundry contributes:
“2D” PDK,
die COST,
Wafers
TSV models, TCE data,
thermal characteristics, …
Materials vendor:
COST, Pkg dimension
thermal characteristics,…
Soft/Hard IP
and/or KGD
IP Partner contributes:
“2D” license & royalties,
models of IP blocks.
And for 3D:
Licensing & KGD COST,
die-level models, …
EDA
Design Tools/Flows
Package,
Interposer,
Substrate
OSAT contributes:
Packaged COST projections for
3D stacks assembly, test, & shipping.
Production test requirements, …
EDA can play an essential role in building the 3D EcoSystem!
The Case for Standards in 3D Design
SOFTWARE
Designers
SYSTEM
Designers
CIRCUIT
Designers
I n t e r o p e r a b i l i t y
Design tools
Design
Rules,
Libraries,
Models
EDA
Vendors
Design
Files and
Test
Programs
Modeling tools
Standards
Standards
to express
material characteristics &
manufacturing capabilities
Manufacturers
Fab, Assembly, Test
for technical
hand-off criteria &
business responsibilities
3D/TSV Modeling & Design Steps
From FABs, OSATs and
materials suppliers
Wafer, TSV,
Interposer,
Passives &
Package’s:
Electrical,
thermal &
mechanical
characteristics
Die- &
Blocklevel
IP
Models
3D System Design
and Partitioning
“2D” PDK
data
and
Major 3D design steps to “hand-off”
at fabless / fablight silicon vendors
“3D”
3D-aware IC Layers
Implementation
PDK
3D-Layers & Stack
Verification for
Design “hand-off”
To Manuf.
Standards for modeling and
Interoperability between tools
data exchange formats between companies
New EDA Opportunities in 3D EcoSystem
H/W Dev. Tools for:
M
O
D
E
L
I
N
G
System Planning & Partitioning
Including die-level IP Reuse
Logical & Physical
3D-aware Implementation
of new design portion(s)
Verification of new design
portion(s) and entire system.
Test program development
Hand-off to manufacturing
S/W Dev. Tools:
C
O
D
E
S
I
G
N
Operating
System
.
Applications
Software
.
.
Drivers
.
.
Field Updates
EDA Opportunities in 3D Design

Modeling tools/flows to expand 2D PDKs to “3D PDKs”


Modify proven 2D tools to make them “3D aware”


3D DFT, die+stack+I/P+passives+pkg co-design, warpage, magnetics,…
Create system-level H/W planning and partitioning tools


PI, SI, noise, temp analysis, TSV strain, P & R ?,…
Create tools for 3D specific new challenges


Capture electrical-, thermal-, magnetic-, mechanical characteristics,…
“Pathfinding” for lowest cost, lowest power, smallest formfactor,…
Create system-level hardware and software co-design tools

System partitioning in H/W and S/W, emulating, debugging, updating,…
-------------------
Create tools for OS-, appl. S/W-, drivers development & debug

Multi- and many-core, handling of very wide busses, error detection and
recovery, managing hardware redundancy (TSVs, memory, logic?, …)
A Closer Look at System Design
EDA vendors say about system-level tools:

They have to be application specific and utilize a high-level of
abstraction to offer significantly higher productivity

Joint development of application-specific tools requires very good
cooperation with the actual users at the EDA customers

The number of system designers is much smaller than the number of
circuit designers
Points above are valid concerns, but keep in mind:

As system complexity and value increase, the need for system-level
tools increases beyond C++ to RTL,… large opportunity for EDA !

Higher abstraction level tools will increase number of system designers

Today’s EDA tools sell per seat for the contract period. Their price is not
tied to the value they create  New business model for system tools?

System designers who implement large “2D SoCs” can benefits from 3D
system tools as well  increases user base and revenues for these tools !

Systems’ software content is increasing and extends systems’ useful life
significantly  Tools for H/W & S/W co-design & S/W development needed!
3D Challenges & Opportunities for EDA
• Incremental EDA features and problems associated with migration to 3D
• Top-down and very broad-brush perspective
• Key challenges are on the System Design Side of things
• Incremental minor
model formats
3D
• Incremental minor
DRC decks
 Design Kits include
2D
Design Rules
DRC/LVS Decks
Spice Models
DFM Kits
Interface to
Manufacturing
Source: Riko Radojcic, Qualcomm
• Minor upgrades of 2D
tools to recognize
incremental features
• Pathfinding tools and estimation
methods, to make it
worthwhile for users
• Standards for Design
Exchange Formats
• New Biz Model, to make it
worthwhile for providers
 Standard physical
RTL 2 GDS design
tools and flow
Physical
Design
•
Private domain of IDMs and
system design entities
System
Design
Discussion Topics
 When will 2½D cross the chasm?
When will 3D …. ?
 Which applications will use 2½D first ? // … 3D/TSVs first ?
 Are EDA vendors jumping into the 3D drivers seat ?
 How are IDMs vs fabless/fablight vendors approaching 3D ?
 Would a different EDA biz model increase support for 3D ?
 Can we jointly define open EDA standards for 3D or do
we want to wait for de-facto (= proprietary) standards ?
 What are bigger opportunities (vs 3D) to grow EDA revenues?
 NEXT technologies: 3D monolithic ICs and Carbon Nanotubes
Thank You !
Cooperation Standards System-level Business Model
[email protected]