Transcript No Slide Title

Semiconductor
Process
Design
Methodology
Market
Segment
Technology
Paradigm
Shifts
Challenges
&
Directions
Electronic
Design
Automation
Research
Figure 0.1 Process: Focus on Change
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Interconnect Delays and
Signal Integrity
Feature Size
1998
2003
Device Count
Designer Productivity
1998
Power &
Signal Integrity
2003
Clock Freq
1998
Figure 0.2 Technology Trends
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2003
10000
1000
Clock Freq
(MHz)
100
chip
10
1u
.8u
.6u
.35u .25u .18u
.13u
.1u
Process Min Geometry
Based on Information provided by Shakhar Borkar, Intel
Figure 0.3 Design Pushing Frequency Through Architecture and Circuit Changes
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1000
100
AMPS
10
1
chip
.1
1u
.8u
.6u
.35u .25u .18u
Process Min Geometry
Based on Information provided by Shakhar Borkar, Intel
Figure 0.4 Power Rises Sharply
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.13u
.1u
Design Size:
Total Transistors
Total Logic Transistors
Chip I/Os
Wiring levels
Scaling:
Target Process for Microprocessors
Chip Size
Frequency:
Local Clock Freq.
Chip Statistics
Chip I/Os:
Wiring levels
Total Interconnect length
200 million
50 million
4000
8
100nm (2003 Starts for 2005 Ship)
520 mm2
3.5 GHz
3rd Harmonic = 9GHz
Slew rate = 150Ghz
4000
8
2840 m/chip
Figure 1.1 Target Chip Data Sheet
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Delay (ns)
1
1 cm Buffered Interconnect
.1
1 mm Interconnect
Device Delay
.01
70
100
130
Process Minimum Geometry (nm)
Figure 1.2 Global and Local Delays vs. Gate-Device Delays
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The Taskforce objective is to find approaches to design larger chips
with fewer engineers while being concerned about more detail. This
report identifies enhancements and modifications to semiconductor
processing, design methodology and electronic design
automation that the Taskforce feels is necessary to reach this
objective.
Figure 1.3 Taskforce Objective
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Active C nf/mm2
1
.1
130
100
Process Minimum Geometry (nm)
Based on Information provided by Shakhar Borkar, Intel
Figure 2.1 Growth in Active Capacitance
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70
Relative
Frequency
3
Densit
3 y
2
2
2
1
1
1
Power
3
130
100
Process Minimum Geometry (nm)
Based on Information provided by Shakhar Borkar, Intel
Figure 2.2 More Supply Current
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70
Power (watt)
Vcc (volt)
Current (Amp)
1000
10
1000
100
1
100
10
.1
10
130
100
Process Minimum Geometry (nm)
Based on Information provided by Shakhar Borkar, Intel
Figure 2.3 Power / Voltage = Current
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•
Semiconductor Process Changes Required for Increased Power
– Additional Metal Layers for Power Planes
– Additional Metal Layers for Shielding
– On Chip Decoupling Capacitors
•
Power Management Design Methodology
– Increase Usage of Gated Clocks
– Staggered Clock
– Self Timed and Asynchronous Design
•
Design Automation Required for Increased Power
– Early Prediction of Power
– Self-Inductive and Mutual-Inductive Effects to Signal Line Avoidance Software.
– Power Dependent Timing Verification
Figure 2.4 Increased Power / Current: Taskforce Recommendations
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Figure 3.1 Gate / Interconnect Delay
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Gate Delay
On Chip Parameter Variability
Average Interconnect Delay
Time of Flight
Interconnect Resistance
3ps
Self Inductance Signal Lines
0.5nh/mm
0.3nh/mm
+/-10%
12ps
5ps/mm
100 ohms/mm
Mutual Inductance signal to signal
Crosscap
0.2pf/mm
Crosscap to Signal lines
Reflections
.6 Cinterconnect / Ctotal
RF antenna
2.5mm
Non--terminated long routes above 9Ghz
Figure 3.2 Delay and Signal Integrity Data
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Contributed by A Kahng
Figure 3.3 Delay Variation
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a
A
b
B
ff
FF
..
.
..
.
Figure 3.4 Signal Interrelationships
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•
Semiconductor Process Changes Required for Signal Integrity and Delay Uncertainty
– Additional Metal Layers for Shielding
– Low mutual capacitance and low mutual inductance between signals including power
•
Signal Integrity Design Methodology
– Hierarchical Design that is Interconnect Centric
– Staggered Signals
•
Design Automation Required for Signal Integrity
– Physical Design that is Signal Integrity Aware
– Multi-Port Delay Models
– Multi-Path Timing Analyzer
– Interconnect Centric Design Tools which emphasize High Level Physical Design.
Figure 3.5 Signal Integrity and Delay Uncertainty: Taskforce Recommendations
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•Avoid problems
•Verify once
•Interconnect centric design
•Tether design changes
Figure 4.1 Guiding Principles
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•After Architecture
•Full Chip Layout
•Forecast Block
Specifications
•Create Blocks
•Actively Avoid Problems
•Add Shielding
•Add Buffers
•Build / Backannotate
Models
•Verify Block
•Verify Chip Using Models
Figure 4.2 Meet in the Middle Design Approach
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ARCHITECTURE
MICRO-ARCHITECTURE
FORECASTING
VERIFICATION
TAPEOUT
CHIP DESIGN
MODEL BUILDER
VERIFICATION
LIBRARY / PROTOTYPES/
GENERATORS/EXPERIENCE
Figure 4.3 Interconnect Centric Design System
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•Budgets / Specifications
•Power Distribution
•Built -in-Test
•Dominant Signal (Such As Clock and
Reset)
•Block Delay Distribution
•Signal Integrity
•Soft Error Control
•Area / Pinout
•Function
•Audit Design vs. Budget
Figure 4.4 Forecasting
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•Estimates
•Experience
•History
•Intellectual Property
•Generators
•Prototyping
•Model Building
•In-place Models Including
Interconnection
•Backannotate Physical Design
Characteristics
•Full Range of Design Parameters
Figure 4.5 Automated Model Builder
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1.00 E+00
Cost per transistor
(cents)
1.00 E-01
1.00 E-02
1.00 E-03
1.00 E-04
Silicon manufacturing
Test equipment
depreciation
1.00 E-05
1.00 E-06
19 19 19
82 85 88
19
91
19 19
94 97
20
00
20 20 20 20
03 06 09 12
Year
arr
Source: Gadi Singer, VTS ‘97 Keynote (Design & Test, Sept., 1997)
Fig 5.1 Test Cost Impact on Product Pricing
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100
10
Silicon speed
OTA
Potential yield
loss
2015
2010
2005
2000
1995
1990
0.1
1985
1
1980
Time in ns
yield loss in percent
1,000
Year
Source: Gadi Singer, VTS ‘97 Keynote (Design & Test, Sept., 1997)
Fig 5.2 Yield Loss due to Guard Banding
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$400
$300
$200
$100
$0
8086
286
386
486
386SL
Product - Source: Intel; from an MCC proposal
Fig 5.3 Cost Per Burn-in Socket Position
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P5
Time
Timetotovolume
Market
ramp
Time
tapeou
Timetotoprod.
Volume
i486 tm)
processor
(
t
Pentium (r)
processor
0
2
4
6
0
0
0
Time to market
(weeks)
8
0
10
0
Source: Carbine and Feltman (Intel) at ITC
‘97
Fig 5.4 Time to Market and Volume Increasing
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Delay vs. VDD Voltage: 5 delay fails, 1 control
35
Delay test failures
31
Good
device
27
23
110 100
90
80
70
60
50
40
30
Latch-latch minimum delay (ns)
Latch-latch minimum delay (ns)
Temperature vs. Delay: 2 delay fails, 1 control
50
Delay test failures
40
Good
device
30
20
3.7
Temperature (deg. C)
3.3
2.9
VDD Voltage (V)
Source: Sematech “Test Methods” Study
Fig 5.5 Temperature and Voltage Stress Identifies Faulty Behavior
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2.5
Tool 2
Tool 1
Interchange
Format 1
Database
Database
Xlator 1
Tool 3
Interchange
Format 2
Database
Xlator 2
Tool 4
Interchange
Format 3
Fig 6.1 Current Systems
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Database
Tool 2
CO Interface
Tool 1
CO Interface
Database
Tool 3
Database
Tool 4
CO Interface
CO Interface
Database
Database
Fig 6.2 Component Object Systems
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•Power Delivery
•Power and Ground Planes
•On chip and/or On MCM Bypass Capacitors
•Signal Integrity Assurance
•Shielding
•Low mutual capacitance and mutual inductance materials
Figure 7.1 Process Modifications
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•Signal Integrity Design Methodology
•Meet-at-the-full-chip level Design Approach
•Hierarchical Design that is Interconnect Centric
•Staggered Signals and Asynchronous Logic
•Rules Based Design
•Constraints
•Top Down Forecasting
•Bottom up Model Building
Figure 7.2 New Design Methodologies
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MICRO-ARCHITECTURE
FORECASTING
CHIP DESIGN
MODEL BUILDER
VERIFICATION
LIBRARY / PROTOTYPES/
GENERATORS/EXPERIENCE
Figure 7.3 Interconnect Centric EDA
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2
450
1.8
400
1.6
350
1.4
300
1.2
250
1
200
0.8
150
0.6
100
0.4
50
0.2
0
V d d (V o lts)
F eatu re S iz e (u m )
500
0
1997
1999
2001
2003
2006
Year
F e a t u re s (u m )
R e la t ive Q
V dd
Figure 8.1 CMOS Charge is Decreasing
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n+
p+
n+
+- +- +++-
p+
n+
+-
n+
+-
+- ++- +-
p+
p+
+-
Oxide Insulator
+- ++-
+-
++-
Substrate
Bulk CMOS
SOI
Figure 8.2 Soft Errors in CMOS and SOI
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