Transcript Document

MODERN ENIAC WP2 Meeting
(WP2-T2.4)
WP2 and Tasks review
Milano Agrate, 2011 Oct. 05
Meeting hosted by Micron
WP2 Review Meeting
Milan, October 05, 2011
Relation among Work Packages
WP2 Review Meeting
Milan, October 05, 2011
2
T2.4 Task (1/2)
•
•
•
•
Task T2.4: Correlation between PV and reliability, reliability modeling
The impact of process variability on existing device reliability degradation models will be clarified.
Aging measure-ments will be performed on test structures: Device degradation mechanisms will
be identified based on silicon, their effect on PV parameters will be characterized and modeled to
allow for a better description of aging during operation.
Partners: AMS, IMEP, UNET, TUW, UNCA, UNGL
UNGL will develop methodologies for the simulation of the statistical impact of NBTI and hot
carrier degradation on the MOSFET characteristics in concert with the statistical variability
sources described in T2.2 and its capture in statistical compact models. UNCA will perform aging
measurements on nano-MOSFET devices focusing on the three main reliability mechanisms: hotcarrier injection, bias-temperature instability and time-dependent dielectric breakdown. The impact
of process variation (e.g. line edge roughness, random dopant distribution, non-homogenity of the
gate dielectric) on the device reliability will be investigated and potential solutions will be
proposed. Aging models will be developed to predict device lifetime dependence on the statistical
fluctuations of geometrical and technological parameters of nano-MOSFET. Model parameters will
be calibrated with the hardware results of aging measurements. UNET will work on methodologies
to design reliability experiments that allow characterizing the impact of PV on test structures,
single cells or simple arrays, on 45nm & 32nm planar CMOS, and on Non-Volatile Memories. It
will include the development of compact models including aging effects. AMS will execute lifetime
measurements necessary for model development and the usage in SPICE simulators in 0.13um,
0.18um and 0.35um CMOS and HV technologies. The objective is to develop silicon based
models for PV and reliability correlation. Lifetime measurements will be performed on appropriate
test structures. Based on that data set, PV-aware parameter degradation models for NBTI and
HCI effects will be developed at TUW. Since in particular degradation caused by NBTI is known to
recover quickly once the stress is removed, emphasis will be put on a proper description of the
dynamical properties of the degradation.
WP2 Review Meeting
Milan, October 05, 2011
3
T2.4 Task (2/2)
• Task T2.4: Correlation between PV and reliability, reliability
modeling (cont’)
• With future technology nodes it is becoming more and more critical
to consider statistical and deterministic variations for ensuring the
design goal at time of manufacturing as well as for the proposed
lifetime. IMEP will investigate based on mixed mode TCAD
simulation and on analytical models the SBD/BD failure occurrence
impact at device level on device characteristics and at elementary
circuit level on subsequent circuit functioning. These studies will be
extended to new device architecture featuring thin silicon film
(MugFET, GAA), which will be benchmarked in term of reliability
robustness to bulk devices. This will require a detailed analysis of
the SBD/BD occurrence and characterization on actual FD-SOI or
GAA devices. The work will be carried out in collaboration with
STF2.
WP2 Review Meeting
Milan, October 05, 2011
4
Reliability: T2.4 Deliverables
Ref
Deliverable/ Contributors
Due date
D2.4.1
Specification of considered degradation effects, modeling
approaches and device parameters (UNGL, TUW)
M6
DONE
D2.4.2
Hardware results of aging measurements available, on planar bulk M24
CMOS technologies (AMS, TUW, UNET, UNCA)
DONE
D2.4.3
Implementation of statistical degradation effects into aging models, M33
hardware calibration of degradation effects (IMEP, AMS, TUW,
UNGL, UNET, UNCA)
Task Leader: [email protected]
WP2 Review Meeting
Milan, October 05, 2011
5
D2.4.1 Considered degradation effects
• Contributions
Effects ->
Technologies
HCI
NBTI
HV mos
AMS,TUW AMS,TUW
65nm cmos
UNCA
45nm cmos
UNGL
UNGL
TDDB
RTN/Trapping/
De-trapping
SBD/BD
UNGL
NVM
UNET, NMX
Thin Si
IMEP
WP2 Review Meeting
Milan, October 05, 2011
6
D2.4.1 Measurements
• Contributions
Degradation
mechanism
Figure
Conditions
Comments
NBTI
VT
VG range
T range
LV HV MOS: Recoverable and permanent
degradation components (AMS/TUW)
HCI
Idlin,
Idsat, VT
VG range
T range
HV MOS: degradation can not be predicted.
Presence on Self-heating and NBTI stress
during measurements (NBTI)
PV effects on
Reliability
Idlin,
Idsat, VT
HV MOS: NBTI/HCI tests on production lots,
and corner lots, and correlation with tests
before stress (AMS/TUW)
Mismatch
65nm: HCI tests and impact on mismatch
(UNCA)
VT, RTN
NVM: impact of program/erase on Trapped
Interface/Oxide charges (IUNET)
WP2 Review Meeting
Milan, October 05, 2011
7
D2.4.1 Modeling approach
Partners
Tasks
AMS-TUW
. Develop a TCAD tool to analyze the HCI behaviour of HV-CMOS transistors
IUNET-NMX
. Refine their tool for 3D simulation of NVM cells under RTN and RDD
.models for the trapping/detrapping process and its impact on VT fluctuation
. Statistical models for SILC simulations
UNCA
.Statistical compact modelling of HCI fluctuation in 65nm technology
IMEP
.TCAD simulation and Compact modeling of SBD/BD effects in MMuG and GAA
mosfets
UNGL
.Validate the GARAND simulations against 45 nm technology devices and
statistical measurements available at ST-F.
.Introduce spatial distribution of the trapped charge in the oxide and channel
region (HCI).
.Introduce energy distribution of the traps in order to be able to simulate
correlations and gate voltage dependence of the trapping.
. Evaluate the possibility to simulate the statistical aspects of Time Dependent
Dielectric Breakdown (TDDB).
. Statistical compact modelling of NBTI, HCI, VT fluctuation (BSIM, PSP)
All
Implementation in RelXpert environment to enable within Design flow:
.Fresh simulation
.Calculation of the aging using some analytical expression
.Degradation of the SPICE parameters and updating the netlist
.Re-simulation with degraded netlist
WP2 Review Meeting
Milan, October 05, 2011
8
T2.4 Review Summary (1/2)
• Activity done so far, with highlights on technical results, and
dissemination
- D2.4.1 deliverable: done
- NBTI and HC data (0.35 µm LV-CMOS & HV-CMOS): available for TCAD simulations
(AMS & TUW), LV NMOS & PMOS (GOX:15 nm), 20V nLDMOS & pLDMOS (GOX: 7 nm)
- Discuss with T2.5 the most interesting devices for the demonstrator, with T2.1 the
process parameters to take into account. (All T2.4 members)
- Initial physics-based analytical model for NBTI to implement in circuit simulator (UNGL)
- Survey of degradation effects (TUW, UGLA)
- Time dependent modeling of degradation for NBTI & HC (TUW, back-up slides)
•
D2.4.2 deliverable (M24): Done
- TCAD reliability simulations focused on LV devices in HV-CMOS process.
- Hot-carrier degradation measurements for analytical & TCAD model developments.
- Threshold Voltage Mismatch Induced by Hot-Carrier in 65 and 45 nm Technology Node.
WP2 Review Meeting
Milan, October 05, 2011
9
T2.4 Review Summary (2/2)
•
Plan for D2.4.3 deliverable (M33):
- Statistical compact Models will be extracted at different levels of NBTI and PBTI (UNGL).
- Time dependence of the statistical compact models will be provided based on NBTI and PBTI models
of trap charge as a function of time. (UNGL)
- Analytical NBTI and HC model developments for LV- & HV-CMOS
- TCAD reliability simulations focused on HV-CMOS technology(AMS, TUW)
- Digital IG noise simulation (UNET)
- All T2.4 members
• Issues :
• Interaction need:
- AMS & TUW: 0.35 µm LV-CMOS & HV-CMOS, D2.4.2 and D2.4.3 (output for T2.5)
- UNET (partner: NMX): NVM, D2.4.2 and D2.4.3
- UNCA (partner: ST-I): 65 nm, D2.4.2 and D2.4.3
- UNGL (partner: STF2): 45 nm CMOS, D2.4.3
- IMEP (partner: STF2): Finfets, MUG, GAA, D2.4.3
WP2 Review Meeting
Milan, October 05, 2011
10
T2.4 Back-up slides
1. NBTI & Hot-Carrier Activities (TUW)
2. Subthreshold Slope Mismatch Induced by Hot-Carrier in 65 and
45 nm Technology Node (UNCA & NXP)
3. Digital IG Noise Simulations (UNET)
4. A Methodology for Simulating the Statistical Aspect of P/NBTI
and Hot-Carrier Degradation (UNGL)
5. Hot-Carrier Lifetime Models for High-Voltage Transistors (AMS)
WP2 Review Meeting
Milan, October 05, 2011
11
1. NBTI & Hot-Carrier Activities
( D2.4.3)
Vienna Universty of Technology (TUW)
WP2 Review Meeting
Milan, October 05, 2011
12
Present/Done Activities: NBTI
• Discrete capture/emission time map (CET) of τc and τe
– Strong bias dependence of τc
– Strong temperature dependence of both τc and τe
– Note: τc = τc(VH) and τc = τc(VL)
WP2 Review Meeting
Milan, October 05, 2011
13
Present/Done Activities: NBTI
• What is the use of CET time map?
– Reconstruct the temporal behavior (jus like Fourier transform)
– Macroscopic version (expectation value)
• Example CET map for an SiON pMOS with EOT = 2.2 nm
WP2 Review Meeting
Milan, October 05, 2011
14
Present/Done Activities: NBTI
• Analytical model for the CET map
– Two bivariate normal distributions for the activation energies
– Parameters bias-dependent
WP2 Review Meeting
Milan, October 05, 2011
15
Present/Done Activities: NBTI
• Analytical model for the CET map
– Allow analytical integration for DC and AC stress
WP2 Review Meeting
Milan, October 05, 2011
16
Present/Done Activities: NBTI
• Examples for analytical NBTI model
– Verified for SiO2, SiON, HfSiO, and HfSiON
WP2 Review Meeting
Milan, October 05, 2011
17
Future Activities: NBTI
• Distribution of activation energies
– Microscopic origin of the effective activation energy distribution
– Must be linked to microscopic defect model
WP2 Review Meeting
Milan, October 05, 2011
18
Present/Done Activities: HCD
• The model
Features of previous approaches
Linking all the levels related to this effect
• A physics-based model contains
Carrier transport module
Module describing the defect build-up
Module for simulation degraded devices
• Carrier transport
Full-band Monte-Carlo device simulator
MONJU
Allows to thoroughly evaluate the DF
For a particular device architecture
WP2 Review Meeting
Milan, October 05, 2011
19
Present/Done Activities: HCD
• The linear drain current degradation
A. Bravaix et al., IRPS-2009
– Idlin0 – current in a “fresh” device, ΔIdlin – its change
– Vt – threshold voltage, ΔVt – its shift
– μ0 – mobility of a “fresh” device, Δμ – mobility change
• Mobility degraded due to Nit
N. Stojadinovic et al., Electron Lett., 1995
– αsc – prefactor
– ΔVt ≈ 0 in our devices
WP2 Review Meeting
Milan, October 05, 2011
20
Present/Done Activities: HCD
• Analytical approach to HCD modeling
– Based on the TCAD version
– Incorporates interplay between single- and multiple-carrier
processes for Si-H bond-breakage
– Controlled by the carrier acceleration integral (AI)
– Average Nit,SE is introduced
– Analytical expression for I(x)
Integratable
Average Nit → analytical
WP2 Review Meeting
Milan, October 05, 2011
21
Present/Done Activities: HCD
• Slopes of the AI peak
– described by Fermi-Dirac derivatives
– on a log-scale
– piecewise functions
• Parameters varying with Vds:
– slope of I2: β
– extension of the ledge I4: x4-x3
– heights: A2, A3, A4
WP2 Review Meeting
Milan, October 05, 2011
22
Present/Done Activities: HCD
• Parameters vs. Vds
–
–
–
–
–
linear dependence on Vds
scattering in parameters:
stochastic noise
from TCAD model
based on Monte-Carlo
• Dependences:
–
–
–
–
useful to interpolate values
and calculate AI
instead of time-consuming
Monte-Carlo method
Analyze impact of statistical
variations on HCD
WP2 Review Meeting
Milan, October 05, 2011
23
Present/Done Activities: HCD
• Average Nit concentration:
– contains components Ji related to Ii
– expressed via exponential integrals
– explicit expressions for Ji:
WP2 Review Meeting
Milan, October 05, 2011
24
Present/Done Activities: HCD
• Representation of the SE-component
– TCAD results ↔ experiment
– Damage produced by the SE-mechanism
– Good agreement between TCAD and analytical models
WP2 Review Meeting
Milan, October 05, 2011
25
Present/Done Activities: HCD
• SE- and ME-contributions are now considered
–
–
–
–
Rather good agreement between:
experiment
TCAD model results
analytical model results
WP2 Review Meeting
Milan, October 05, 2011
26
Future Activities: HCD Model
• Oxide thickness varies:
– Tox = 0.4, 0.6, 0.8, 1.0, 1.2, 1.4, 1.6, 1.9 Tn
– Tn – nominal thickness
WP2 Review Meeting
Milan, October 05, 2011
27
2. Subthreshold Slope Mismatch Induced by
Hot-Carrier in 65 and 45 nm Technology Node
(Ref.: D2.4.2)
Universty of Calabria (UNCA)
in collaboration with NXP
WP2 Review Meeting
Milan, October 05, 2011
28
PURPOSE
To characterize and to model the
HC-induced subthreshold slope variability
in 65 nm and 45 nm technology node
WP2 Review Meeting
Milan, October 05, 2011
29
Devices Under Test
10
-5
-5
10
-7
65nm
45nm
ID L/W (A)
10
10
-7
10
-9
10
-9
-11
10
-11
10
-13
10
IT=200nA
Gm Max VT
10
Gm Max VT
-13
0.0
0.5
1.0 0.0
0.5
1.0
Gate Voltage (V)
The reported statistical analysis is based on a large overall sample
population of one thousand transistors
WP2 Review Meeting
Milan, October 05, 2011
30
Modeling of HC-indiced Subthreshold Slope
Variability
HC stress causes an increase in the interface state density Dit and thus in the
interface capacity Cit which induces a change in S
Defect depassivation is assumed to be a Poisson process
 S  2 K HC ln10 
q  S 
Cox WL
KHC parameter takes into account for the non-uniform defect depassivation
along the channel direction
WP2 Review Meeting
Milan, October 05, 2011
31
Model Suitability
-1
VDS stress voltage (V)
10
-2
10
-3
10
-4
10
-5
VDS stress voltage (V)
1.7
1.8
1.9
10
10
2
10
-2
10
-3
10
-4
10
-5
10 10
1
10
2
10
10
-2
10
10
-2
10
-3
10
-4
65nm
-3
KHC=2.46
KHC=1.51
LINEAR
65nm
3
-1
45nm
2.0
2.2
2.4
45nm
1
10
 (SHC) (V/dec)
Median S (V/dec)
10
3
10
-4
10
Stress Time (s)
-4
10
-3
10
-2
-4
-3
10
10
Median S (V/dec)
10
-2
10
Experimental data are well fitted by the proposed model, where median S is
used as an input and KHC is extrapolated by interpolation of experimental data
The slope of this plot is very close to 0.5, hence confirming the hypothesis of
Poisson process
WP2 Review Meeting
Milan, October 05, 2011
32
-1
Impact of the HC-Induced Variability on the
Overall Variability
stress voltage
VDS=1.7V
5
stress voltage
VDS=1.9V
Fresh pairs
Stressed Pairs
HC mismatch
4
(S) (mV/dev)
stress voltage
VDS=1.8V
stress voltage
VDS=1.7V
4
2.6mV/dec
(S) (mV/dev)
5
3
2
1
stress voltage
VDS=1.9V
stress voltage
VDS=1.8V
Fresh pairs
Stressed Pairs
HC mismatch
3
1.5mV/dec
2
1
45nm (a)
0
1
10
2
10
3
1
10 10
2
10
3
1
10 10
2
10
65nm (b)
3
10
0
1
10
Stress Time (s)
2
10
3
1
10 10
2
10
3
1
10 10
2
10
3
10
Stress Time (s)
A significant increase of the overall S mismatch is observed for both technologies
WP2 Review Meeting
Milan, October 05, 2011
33
Correlation between VT and S
SHC (V/dec)
0.02
45nm
65nm
LINEAR
0.02
0.01
0.01
0.00
0.00
-0.01
-0.01
Corr. Coeff. = 0.49
-0.02
-0.05
0.00
Corr. Coeff. = 0.55
0.05
0.00
-0.02
0.05
VT,HC (V)
Correlation coefficient is around 0.5 for both technologies
WP2 Review Meeting
Milan, October 05, 2011
34
3. Digital IG noise simulations
( D2.4.3)
Consorzio Nazionale Interuniversitario per la Nanoelettronica
(UNET)
WP2 Review Meeting
Milan, October 05, 2011
35
Digital IG Noise Simulations
•
Physical model reproducing
digital IG fluctuations observed in
ultra-thin dielectrics after SBD
Current fluctuations are modeled
assuming that some traps in the
percolation path switch between
two unstable configurations,
corresponding to neutral and
negatively charged O vacancies.
100
Gate Current [A]
•
experiment
3.3V
3.3V
simulations
10
2.7V
2.7V
1
3.0V
3.0V
0.1
1.8V
1.8V
1.5V
1.5V
0.01
0
100
200
300
0
time [s]
100
200
time [s]
Ref: L. Morassi et al, “ A
Physical Model for postbreakdown digital gate
current noise,”
submitted to IEEE
Electron Device Letters,
2011
WP2 Review Meeting
Milan, October 05, 2011
36
300
4. A Methodology for Simulating the Statistical
Aspect of P/NBTI and Hot-Carrier Degradation
( D2.4.3)
The University of Glasgow (UNGL)
WP2 Review Meeting
Milan, October 05, 2011
37
Purpose
• We developed a methodology for simulating the
statistical aspect of P/NBTI and hot carrier
degradation in 32nm RVT N/PMOS.
• Random trapped charges due to P/NBTI stress
are assigned to interface degradation.
• The threshold-voltage shift is observed and its
variations are analyzed.
WP2 Review Meeting
Milan, October 05, 2011
38
3-D Simulation Method
• The N/PMOS are first
calibrated both in
doping profiles and
electrical
characteristics.
• After stress, the traps
are randomly assigned
at interface according
to local nominal trap
sheet density.
WP2 Review Meeting
Milan, October 05, 2011
39
Device Degradation under Stress
Under PBTI/PBTI stress, the interface trapped charge accumulates,
leading to threshold-voltage shift and device performance
degradation.
WP2 Review Meeting
Milan, October 05, 2011
40
PBTI/NBTI Variability
• NMOS
• PMOS
4
2
0
-2
Trap Density (cm )
1E11
5E11
1E12
-2
-4
0
0.05
VT (V)
0.1
Normal Quantiles
Normal Quantiles
4
2
0
-2
Trap Density (cm )
1E11
5E11
1E12
-2
-4
0
0.1
0.05
|VT| (V)
Both number and placement of traps varies, which leads to
variation of PBTI/NBTI effects.
WP2 Review Meeting
Milan, October 05, 2011
41
0.15
Trap Density Dependence
The threshold-voltage shift is proportional to trap density and its
standard deviation is proportional to the sqrt of trap density. Both
are proportional to EOT. PMOS EOT is slightly larger than NMOS.
WP2 Review Meeting
Milan, October 05, 2011
42
5. Hot-Carrier Degradation Measurements
(Ref.: D2.4.2)
0.35 µm HV-CMOS Technology
- LV-NMOSI, LV-NMOSIM
- NMOSI20T
- PMOS20T
austriamicrosystems AG
WP2 Review Meeting
Milan, October 05, 2011
43
Proposal for a Lifetime Model for High-Voltage Devices
1. Kirk effect: change of location of maximum impact ionisation: depending on gate-voltage.
2. Occurance of multiple locations of significant impact ionisation: depending on bias.
3. Electron injection, hole injection, interface trap generation simultaneously.
4. Self heating.
 No generally accepted HC model is available.
 Formulation of a HC model where Vg and T is an additional parameter:
 IB

 I 
  C (Vg , T )   DS 
I DS
 (Vg )
Modified Hu- model, empirical
WP2 Review Meeting
Milan, October 05, 2011
44
NMOSIM: Cross Section
WP2 Review Meeting
Milan, October 05, 2011
45
LV-NMOSIM: Transfer Curves
5.0E-03
Drain Current, abs. value (A)
4.5E-03
VDS=0.1 V for Lg=0.5 µm
VGstress=2 V and VDstress=7 V
Stress time: 1x105 sec
4.5E-04
Drain Current, abs. value (A)
4.0E-04
4.0E-03
3.5E-03
3.0E-03
2.5E-03
2.0E-03
fresh
stressed
1.5E-03
1.0E-03
5.0E-04
3.5E-04
0.0E+00
0
3.0E-04
1
2
3
4
Gate-Source Voltage
2.5E-04
VDS=5.0 V for Lg=0.5 µm
VGstress=2 V and VDstress=7 V
Stress time: 1x105 sec
2.0E-04
1.5E-04
fresh
stressed
1.0E-04
5.0E-05
0.0E+00
0
1
2
3
4
5
6
Gate-Source Voltage
WP2 Review Meeting
Milan, October 05, 2011
46
5
6
LV-NMOSIM: Output Curves, Degadation versus Stress Time
Degradation (%)
100.0
Output curves
VGstress=2 V and VDstress=7 V
Stress time: 1x105 sec
Idlin
Vth
Idsat
10.0
1.0
5.0E-03
fresh
stressed
Drain Current, abs. value (A)
4.5E-03
4.0E-03
0.1
1.0E+01
3.5E-03
3.0E-03
4
2.5E-03
ce Voltage
2.0E-03
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
Stress Time (s)
5
6
Degradation versus stress time
VGstress=2 V and VDstress=7 V
1.5E-03
1.0E-03
5.0E-04
0.0E+00
0
1
2
3
4
5
6
Drain-Source Voltage
WP2 Review Meeting
Milan, October 05, 2011
47
1.0E+07
LV-NMOSIM: Lifetime-Substrate Current, Ionization-Rate
and Lg Effects on the Lifetime
1.0E+09
Id * lifetime Idlin (s)
1.0E+08
Lifetime versus substrate current
1.0E+07
L=2um
1.0E+07
L=1.2um
1.0E+06
1.0E+05
L=0.8um
1.0E+04
L=0.5um
1.0E+03
10% lifetime Idlin (s)
1.0E+06
1.0E+02
1.0E+01
1.0E-02
1.0E+05
y = 1E+14x
1.0E-01
1.0E+00
-5.8222
abs(Ibulk / Idrain)
1.0E+04
Id x lifetime versus ionization-rate
Ionization-rate and Lg effects on the lifetime
1.0E+03
1.0E+02
1.0E+01
1.0E+00
1.0E+01
1.0E+02
1.0E+03
abs(Ibulk)
WP2 Review Meeting
Milan, October 05, 2011
48
LV-NMOSIM: Charge Pump Measurements
Time evolution of the Icp versus Vgh
Interface state density at the channel region
WP2 Review Meeting
Milan, October 05, 2011
49
HV-NMOS (NMOSI20T) and HV-PMOS (PMOS20T)
NMOSI20T
PMOS20T
WP2 Review Meeting
Milan, October 05, 2011
50
NMOSI20T: Id x Lifetime versus Ionization-Rate
WP2 Review Meeting
Milan, October 05, 2011
51
PMOS20T: Small Hot-Carrier Degradation
Vg=-1.6V
Vg=-1.9V
WP2 Review Meeting
Milan, October 05, 2011
Vg=-3.6V
52
Corner Split on Isolated NMOS Transistor (NMOSI)
NMOSI corner specification
Standard (2)
Worst case
power (5)
Worst case
speed (8)
Worst case
one (11)
Worst case
zero (14)
Leff N/P typ.
Vt NMOS typ.
Vt PMOS typ.
Leff N/P <
Vt NMOS <
Vt PMOS <
Leff N/P >
Vt NMOS >
Vt PMOS >
Leff N/P typ.
Vt NMOS <
Vt PMOS >
Leff N/P typ.
Vt NMOS >
Vt PMOS <
4
7
8
9
10
11
12
x
x
x
x
x
x
Stage
Description
Recipes
1
2
3
Vt implant
BF2, 70K, 7.7E12
x
x
x
5
6
BF2, 70K, 7.4E12
BF2, 70K, 8.0E12
poly 1 mask
DI-CD = 0.40µm
DI-CD = 0.37µm
DI-CD = 0.44µm
x
x
x
x
x
x
x
x
x
x
x
x
x
WP2 Review Meeting
Milan, October 05, 2011
x
x
53
13
14
15
x
x
x
x
x
x
Effective Channel-Length versus Corner Lots
0.44
Std
Worst case power
0.43
Worst case speed
0.42
Worst case 1
Worst case 0
Leff [um]
0.41
0.4
0.39
0.38
0.37
0.36
0.35
0.34
0
2
4
6
8
10
12
14
16
Wafer Number
WP2 Review Meeting
Milan, October 05, 2011
54
Idlin-Shift after 150 sec Stress of Corner Lots
40
Std
Idlin Shift @ 150s [%]
35
Worst case power
Worst case speed
30
25
20
15
10
1.5E-04
1.6E-04
1.7E-04
1.8E-04
1.9E-04
2.0E-04
2.1E-04
2.2E-04
2.3E-04
Idlin @ t0 [A]
WP2 Review Meeting
Milan, October 05, 2011
55
Idsat-Shift after 150 sec Stress of Corner Lots
3
Std
2.5
Worst case power
IDsat Shift @ 150s [%]
Worst case speed
2
1.5
1
0.5
0
0.0051
0.0052
0.0053
0.0054
0.0055
0.0056
0.0057
0.0058
0.0059
0.006
0.0061
IDsat @ t0 [A]
WP2 Review Meeting
Milan, October 05, 2011
56
Conclusions
D2.4.1: done
- Specification of considered degradation effects, modelling approaches and device
parameters
- NBTI and HC data (0.35 µm LV-CMOS & HV-CMOS): available for TCAD simulations
- Initial physics-based analytical model for NBTI to implement in circuit simulator
- Time dependent modeling of degradation for NBTI & HC
D2.4.2 (M24): done
- TCAD reliability simulations focused on LV devices in HV-CMOS process
- Hot-carrier degradation measurements for analytical & TCAD model developments
- Threshold Voltage Mismatch Induced by Hot-Carrier in 65 and 45 nm Technology Node
D2.4.3 (M33): on going
- Statistical compact Models will be extracted at different levels of NBTI and PBTI.
- Time dependence of the statistical compact models will be provided based on NBTI and
PBTI models of trap charge as a function of time
- Analytical NBTI and HC model developments for LV- & HV-CMOS
- TCAD reliability simulations focused on HV-CMOS technology
- Digital IG noise simulation
WP2 Review Meeting
Milan, October 05, 2011
57