Transcript SILICON PROCESSING – FABRICATION YIELD

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SILICON PROCESSING – FABRICATION YIELD
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CHIP DESIGN
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SRITEJA TARIGOPULA
SUBMITTED TO
DR. ROMAN STEMPROK
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Overview of Silicon Processing
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An integrated circuit (IC) consists of several patterned
layers of materials to form FETs and interconnects
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In a modern process :
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Minimum feature size < 0.12µm
Individual chips with more than 100 million FETs
The techniques needed to fabricate chips of this
sophistication have been developed over several decades at
tremendous cost
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Silicon Processing - Wafers
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Si ICs are created on large
circular sheets of Si called
wafers
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Si IC is ~ 1 cm on a side
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100-300mm in diameter
~ 0.7 mm thick
Many ICs on a single wafer
Location of an IC on a wafer is
called a die site
A flat on the wafer is used as a
reference plane to form a grid
for die placement
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Silicon Processing - Wafers
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The manufacturing capacity of a chip factory is measured
by the number of wafer starts per week
The number of wafer starts indicates how many “fresh”
wafers are introduced into the fabrication sequence
Wafers are processed in groups, and it typically takes
several weeks for a lot to pass through the entire
processing line
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Silicon Processing – Fabrication Yield
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Not every die site on the Si wafer produces a functional
circuit
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Due to many factors inherent in the complexity of the Si processing
To quantify problem, chip manufacturers use the concept
of fabrication yield Y ;
Y = [NG / NT] x 100%
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NG = number of good functional sites
NT = total number of sites on wafer
High yield values are critical for IC economic stability
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Silicon Processing – Fabrication Yield
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Yield analysis is based on predicting the yield Y of a
particular IC process
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very specialised aspect of VLSI manufacturing
requires thorough understanding of all aspects of Si processing
Yield analysts attempt to optimise Y for a given IC design
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work closely with groups on manufacturing line
also work with specialist wafer analysis groups
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Silicon Processing – Effect of die area on yield
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A variable that is critically important to increasing the yield
is the area of the die Adie
The total die sites NT on a wafer of diameter d is found as :
NT = (d - de)2 / 4Adie
 de = wasted edge distance from placing rectangular die onto round
wafer
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Empirical analysis shows that large area die are plagued by
smaller yields
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Silicon Processing – effect of die area on yield
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Defects on the wafer can result in circuit failure and
influence Y
The average number of defects per cm2 is denoted by the
parameter D and quantifies the wafer “perfection”
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for modern IC production D is typically ~ 1 cm-2
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For isolated defects :
Y = exp[-(AdieD)]
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For clustered defects :
Y = [1 - (AdieD)/c]c
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c = empirical parameter that characterises cluster structure
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Silicon Processing – Economic Factors
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For economic survival, a Si chip manufacturing plant must be
profitable : profit-per-chip = Csell - Cchip is not easy to estimate
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Cchip = chip production
costs
Cchip includes
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Materials
personnel salaries
(design, manufacture,
test etc)
overheads (electricity,
water, taxes etc)
initial plant commission
~ $1-3 billion !!
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Csell = chip selling price
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all direct and indirect costs
fraction of plant debt
Csell must however be at level that
customers will pay
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high chip demand  Csell 
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“whatever market will bear”
low chip demand  Csell 
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Withdraw product?
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Silicon Processing – Economic Factors
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Notice also that Csell tends to decrease with time !
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Hottest new microprocessors eventually become basement bargains
no problem to IC manufacturer provided initial engineering costs
are recouped
original IC design can be very expensive
A helpful factor in IC manufacturing profitability is that as
time progresses :
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Cchip  Cmaterials
for CMOS Si is very cheap compared to alternatives such as III-Vs
keeping product lines operative for many years therefore improves
overall profitability
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Refrences
 Introduction
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to VLSI Circuits and Systems, by John
P.Uyemura
 D.Morgan and K.Board, “An Introduction to
Semiconductor Microtechnology”, J.Wiley & Sons, 1988
 http://www.personal.dundee.ac.uk/~dmgoldie/teaching/eg4
013/lectures/1
 http://www.stanford.edu/class/ee271/stick_to_layout/stick_
to_layout.html
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Thank you…
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