Transcript PowerPoint Presentation: EE5324-Intro

EE 5301 – VLSI Design Automation I
Part I: Introduction
Kia Bazargan
University of Minnesota
Fall 2006
EE 5301 - VLSI Design Automation I
I-1
Administrative Issues
• Class
 Time and venue: _MW 4:40pm - 5:55pm, ME212 _
 Web page:
o http://www.ece.umn.edu/users/kia/Courses/EE5301
o http://webct.umn.edu/ (requires x.500 ID & pwd)
o !!!! Check the class web page & discussion group regularly !!!!
 Textbook:
Sadiq M. Sait, Habib Youssef, "VLSI Physical Design Automation:
Theory and Practice", World Scientific Publishing Company; 1st
edition (November 15, 1999)
• Grades





Fall 2006
30%
10%
10%
40%
10%
homework
presentations / papers
quizzes
two open book midterms: Mon Oct 16, Wed Nov 29
Final project. Due Wed Dec 6
EE 5301 - VLSI Design Automation I
I-2
Administrative Issues (cont.)
• Personnel
 Instructor: Kia Bazargan
o Email: [email protected]
o Phone: (612) 625-4588
o Office: EE/CSci 4-159
o Office hours: __MW 3:30-4:30pm __
 TA: ___________________
o Email: ___________________________
o Phone: _____________________________
o Office: ______________________________
o Office hours: __________________________
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EE 5301 - VLSI Design Automation I
I-3
Administrative Issues (cont.)
• Policies
 Homework must be received before class starts (hardcopy) or
before 4:30pm (electronic) on the due date
o Three days of grace period for the whole semester
o After the grace period is used, > 10 minutes late  0% of the grade
 Zero tolerance for cheating
 Collaboration OK, copying NOT OK
 Include ID on all homework, exams, etc.
 No extra work for extra credit
 Check class web pages regularly, students are responsible for
checking discussion threads and announcements regularly
 Subscribe to the class mailing list (instructions on the web page)
Fall 2006
EE 5301 - VLSI Design Automation I
I-4
Online Slides
• Slides are posted on the web
 Handouts posted as .pdf files
 Powerpoint slides provided too
o NOTE: some slides are animated (like this one)
o Click on the slide to see the animation
o Click once more.
o Note: some slides have notes! (like this one)
o Some slides contain text that is not printed in the handouts,
but animated. These are left for you to fill out in the handouts.
An example is shown below (animated: click to see)
This is a sample text, not printed, but animated
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I-5
References and Copyright
• Textbooks referred (none required)
 [Mic94] G. De Micheli
“Synthesis and Optimization of Digital Circuits”
McGraw-Hill, 1994.
 [CLR90] T. H. Cormen, C. E. Leiserson, R. L. Rivest
“Introduction to Algorithms”
MIT Press, 1990.
 [Sar96] M. Sarrafzadeh, C. K. Wong
“An Introduction to VLSI Physical Design”
McGraw-Hill, 1996.
 [She99] N. Sherwani
“Algorithms For VLSI Physical Design Automation”
Kluwer Academic Publishers, 3rd edition, 1999.
Fall 2006
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References and Copyright (cont.)
• Slides used: (Modified by Kia when necessary)
 [©Sarrafzadeh] © Majid Sarrafzadeh, 2001;
Department of Computer Science, UCLA
 [©Sherwani] © Naveed A. Sherwani, 1992
(companion slides to [She99])
 [©Keutzer] © Kurt Keutzer, Dept. of EECS,
UC-Berekeley
http://www-cad.eecs.berkeley.edu/~niraj/ee244/index.htm
 [©Gupta] © Rajesh Gupta
UC-Irvine
http://www.ics.uci.edu/~rgupta/ics280.html
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EE 5301 - VLSI Design Automation I
I-7
What is This Course All About?
• Prerequisite
 C / C++ programming experience
 Kia will try to provide tutorials
• What is covered?
 Basic algorithms, complexity theory
 Integrated circuit (IC) Design flow
 Computer Aided Design (CAD) tool development for
Very Large Scale Integration (VLSI)
 Lots of programming!
• Next slides:
 Overview of IC design steps
 Related courses at U of M
 Outline of this course
Fall 2006
EE 5301 - VLSI Design Automation I
I-8
IC Products
• Processors
 CPU, DSP, Controllers
• Memory chips
 RAM, ROM, EEPROM
• Analog
 Mobile communication,
audio/video processing
• Programmable
 PLA, FPGA
• Embedded systems
 Used in cars, factories
 Network cards
• System-on-chip (SoC)
Fall 2006
EE 5301 - VLSI Design Automation I
Skip
econ
Images: amazon.com
I-9
IC Product Market Shares
Source: Electronic Business
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I-10
The Inverted Pyramid
Electronic Systems > $1 Trillion
Semiconductor > $220 B
CAD $3 B
Fall 2006
EE 5301 - VLSI Design Automation I
[©Keutzer] I-11
Semiconductor Industry Growth Rates
Source: http://www.icinsight.com/ (McClean Report)
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I-12
More Demand for EDA
CAE = Computer Aided Engineering
Source: http://www.edat.com/edac
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I-13
Growth in System Size
CAGR = Compound Annual Growth Rate
Source: http://www.edat.com/edac
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I-14
Example: Intel Processor Sizes
Silicon Process 1.5m
Technology
1.0m
0.8m
0.6m
0.35m 0.25m
Intel386TM DX
Processor
Intel486TM DX
Processor
Pentium® Processor
Pentium® Pro &
Pentium® II Processors
Source: http://www.intel.com/
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I-15
Moore’s Law
Transistors
Microprocessors
10M
80386
68020
68000
1M
100K
10K
PPC603
Pentium
80486
Pentium Pro
PPC601
MIPS R4000
68040
8086
4004
8080
1K
10x/6 years
100
10
1
1975
Fall 2006
1980
1985
1990
EE 5301 - VLSI Design Automation I
1995
[©Keutzer] I-16
NRTS: Chip Frequencies
Clock speed GHz
11
9
7
5
3
1
0
1997
1999
2001 2003
2006 2009
2012
On-chip, local clock, high performance
On-chip, global clock, high performance
Fall 2006
EE 5301 - VLSI Design Automation I
[©Keutzer] I-17
Increasing Device and Context Complexity
• Exponential increase in device
complexity
• More complex system contexts
 System contexts in which devices are
deployed (e.g. cellular radio) are increasing
in complexity
Complexity
 Increasing with Moore's law (or faster)!
• Require exponential increases in design
productivity
We have exponentially more transistors!
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EE 5301 - VLSI Design Automation I
[©Keutzer] I-18
Deep Submicron Effects




Crosscoupled capacitances
Signal integrity
Resistance
Inductance
DSM Effects
• Smaller geometries are causing a wide
variety of effects that we have largely
ignored in the past:
Design of each transistor is getting more difficult!
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EE 5301 - VLSI Design Automation I
[©Keutzer] I-19
Heterogeneity on Chip
• Greater diversity of onchip
elements




Processors
Software
Memory
Analog
Heterogeneity
More transistors doing different things!
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EE 5301 - VLSI Design Automation I
[©Keutzer] I-20
Stronger Market Pressures
• Decreasing design window
• Less tolerance for design
revisions
Time-to-market
Exponentially more complex, greater design risk,
greater variety, and a smaller design window!
Fall 2006
EE 5301 - VLSI Design Automation I
[©Keutzer] I-21
A QuadrupleWhammy
Complexity
Time-to-market
Heterogeneity
DSM Effects
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[©Keutzer] I-22
How Are We Doing?
10,000,000
1,000,000
100,000
10,000
1,000
100,000
Productivity
gap
10,000
1,000
100
2005
2001
1997
1989
1981
1993
100
21% / Yr. compound
productivity growth rate
10
10
Role of EDA: close the productivity gap
Fall 2006
Productivity
Trans. / Staff . Month
58% / Yr. compound
complexity growth rate
EE 5301 - VLSI Design Automation I
2009
1,000,000
100,000,000
1985
Logic transistors per chip
(K)
10,000,000
Source:
SEMATECH
[©Keutzer] I-23
Evolution of the EDA Industry
Results
(design productivity)
What’s next?
Synthesis – Cadence, Synopsys
Schematic entry – Daisy, Mentor, Valid
Transistor entry – Calma, Computervision, Magic
McKinsey S-Curve
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EE 5301 - VLSI Design Automation I
Effort
(EDA tool effort)
[©Keutzer] I-24
IC Design Steps (cont.)
Specifications
Fall 2006
High-level
Description
Functional
Description
Behavioral
VHDL, C
Structural
VHDL
EE 5301 - VLSI Design Automation I
Figs. [©Sherwani] I-25
IC Design Steps (cont.)
High-level
Description
Specifications
Physical
Design
Placed
& Routed
Design
Packaging
Fall 2006
Functional
Description
Synthesis
Technology
Mapping
Gate-level
Design
Fabrication
EE 5301 - VLSI Design Automation I
Logic
Description
X=(AB*CD)+
(A+D)+(A(B+C))
Y = (A(B+C)+AC+
D+A(BC+D))
Figs. [©Sherwani] I-26
The Big Picture: IC Design Methods
Design
Methods
Cost /
Development
Time
Quality
# Companies
involved
Full Custom
Standard Cell
Library Design
ASIC – Standard
Cell Design
RTL-Level Design
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Optimization: Levels of Abstraction
• Gate-level
 Reduce fan-out, capacitance
 Gate duplication, buffer insertion
• Layout / Physical-Design
 Move cells/gates around to
shorten wires on critical paths
 Abut rows to share power /
ground lines
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EE 5301 - VLSI Design Automation I
Level of detail
 Encoding data, computation
scheduling, balancing delays of
components, etc.
Effectiveness
• Algorithmic
I-28
Full Custom Design
Structural/RTL Description
Component Design
Ctrl
Mem
Reg
File
Comp.
Unit
Place & Route
I/O
...
PLA
comp
RAM
A/D
Floorplan [©Sherwani]
Layouts [© Prentice Hall]
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Full Custom Design Example
I/O Pad
Via
comp
PLA
I/O
Metal2
Metal1
Macro
cell
design
RAM
A/D
Glue logic
(standard
cell design)
[©Sherwani]
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ASIC Design
HDL Programming
Structural/
RTL Description
P_Inp: process (Reset, Clock)
begin
if (Reset = '1') then
sum <= ( others => '0' );
input_nums_read <= '0';
sum_ready <= '0';
Ctrl
Mem
Reg
File
Comp.
Unit
add82 : kadd8 port map (
a => add_i1, b => add_i2,
ci => carry, s => sum_o);
Mult_i1 <= sum_o(7 downto 0);
D
C
A
D
C
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C
C
C
C
B
C
D
C
B
B
Cell library
A
C
EE 5301 - VLSI Design Automation I
B
D
Floorplan [©Sherwani]
I-31
ASIC (Standard Cell) Design Example
VDD
Metal1
D
GND
Metal2
C
C
C
A
Cell library
B
C
B
A
C
Cell
D
D
C
C
C
D
C
B
B
Placement [©Sherwani]
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Where Is This Course in the Big Picture?
• VLSI related courses:
VLSI CAD
EE 5301
VLSI Design
EE 5323
VLSI Design
Automation I
VLSI Design I
EE 5302
EE 5324
VLSI Design
Automation II
VLSI Design II
EE 5333
Analog
Integrated Circuit
Design
Fall 2006
EE 5301 - VLSI Design Automation I
Others
EE 4301
Digital Design
With Programmable
Logic
EE 5329
VLSI Digital
Signal Processing
Systems
EE 5549
Digital
Signal Processing
Structures for VLSI
I-33
Course Outline
• Basic algorithms and complexity theory
 Circuit representations
 Classes of problems (P, NP)
 Classes of algorithms (dynamic programming, network
flow, greedy, linear programming, etc.)
 Graph algorithms
• High-level synthesis
 Converting high-level languages to RTL
 Scheduling operations
 Allocating functional resources (adders, multipliers,
registers, etc.)
 Register minimization
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Course Outline (cont.)
• Partitioning
 FM, KL, hMetis algorithms
• Floorplanning
 Slicing, non-slicing floorplans
 Simulated annealing floorplanning algorithms
• Placement / Packing
 Force-directed
 Simulated annealing
 Quadratic placement
• Global / detailed routing
 Maze routing, line-search, Steiner trees, channel
routing,
Fall 2006
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To Probe Further...
• International Technology Roadmap for
Semiconductors (ITRS)
 http://public.itrs.net/
• SEMATECH
 http://www.sematech.org/
• Textbook
 Chapters 1, 2
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