Transcript No Slide Title

ECNG 1014: Digital Electronics
Combinational Circuits
1
Logic Device Classification
Combinational
Circuit output is a function only
of the current inputs eg., AND
gates, decoders
Small Scale Integration (SSI)
Integrated circuit uses only a few gates
(20 or less). Typically provides only basic
gate functions
Sequential
Circuit output is a function only
of the current inputs AND past
inputs i.e. the circuit has
memory. Eg. counters
Medium Scale Integration (MSI)
IC uses 20-200 gates to provide common
higher level functions such as decoding,
multiplexing, counting etc.
Very Large Scale Integration
(VLSI)
IC with over 106 transistors or
more which realises the highest
level of logic functionality.
Examples: Pentium level
processors (50 mil xsistors!),
FPGAs etc.
Large Scale Integration (LSI)
Ics have 200-200K gates ( 400K
transistors) or more to realise still higher
functions such as small memories and
microprocessors, PLDs, CPLDs etc.
Device delay (and cost) goes up
with complexity
2
Design Procedure for Combinational Circuits
• State the problem in combinational terms.
• Determine the required inputs and outputs
• Derive the truth table.
• Simplify the output expressions using
Boolean laws or k-maps.
• Implement the output expressions with logic
gates.
• Design example: Implement a logic circuit
that detects if an unsigned 4-bit number is
prime.
3
Combinational Logic Using MSI and LSI devices
• Commercial ICs can perform complex functions using a
single IC of type MSI or LSI, their characteristics are
described in Logic data book (http://www.ti.com,
semiconductor logic).
4
TTL Device Number
Description
7483
4-bit adder with fast carry
7485
4-bit magnitude comparator
74139
2-line-to-4-line decoder/demultiplexer
74137
3-line-to-8-line decoder/demultiplexer
74159
4-line-to-16-line decoder/demultiplexer
74145
BCD-to-Decimal encoder
74147
Priority encoder
74151
8 x 1 multiplexer
74150
16 x 1 multiplexer
74184
BCD-to-binary converter
74280
9-bit odd/even parity generator
5
Decoders (5.4.1-5.4.5)
General
decoder
structure
• A decoder is a MIMO
device that maps an
input code to a
different unique
output code, I.e. the
mapping is 1-to-1
• Typically n inputs, 2n
outputs 2-to-4, 3-to-8, 4to-16, etc
• Most common: Binary
Decoder maps each nbit input to assert only 1
Also: 7-segment and BCD decoders
of 2n outputs
6
Binary decoder applications
• Microprocessor memory systems
– selecting different banks of memory
• Microprocessor input/output systems
– selecting different devices (printer, serial, video etc)
• Microprocessor instruction decoding
– enabling different functional units within the uP.
• Memory chips
– enabling different rows of memory depending on
inputted address
• Identifying or selecting various circuit options. Can
also be used for logic synthesis since each output actually
represents a unique minterm of the inputs…….
7
Binary 2-to-4 decoder
Enable input
x = don’t care.
Once Enabled, ONLY the k’th logic output (k:0, 1,..2n-1) is
asserted when the input binary word satisfies:
I1I0 = k … the k’th minterm!!
=>
¡¡
Y0 = mo, Y1=m1, … Yi=mi !!
8
SO… can use to synthesise all logic functions of n
variables!!
E.g. Realise F=X,Y(0,3) using a 74x139 2-4 decoder
The 1/2 => the 74139 has TWO (independent) decoders.
Only using 1 of them
Bubble <=>
Active low enable
0
F
Y
X
Select inputs: B is the MSB
in the select word i.e. BA
Most decoders use Active Low outputs
=> faster
9
Complete 74x139 Decoder
All Inputs buffered
to minimise loading
10
How do we get a larger decoder?
Cascade smaller ones….
Use MSB(‘s) to
select one
decoder (for one
part of the Truth
Table)
b2
b0
b1
Use lower SB’s
to select the
output
DEC0_L
DEC1_L
DEC2_L
DEC3_L
Upper
half of TT
(b2=0)
DEC4_L
DEC5_L
DEC6_L
DEC7_L
Lower half
of TT
(b2=1)
The “_L “ is a standard nomenclature for
an active low signal line
11
Or.. We can use an off-the-shelf device, if available
74x138 3-to-8-decoder
EN = (G1)(G2A)’(G2B)’
C is MSB
12
13
8
A0-13
MC6809uP
To all memory
data pins
8
Data(8)
8
A0-13
To all memory
address pins
A0-13
14
Address (16)
Control
The decoder selects
only 1 of the 4
banks at a time for
data bus connection.
2-4
Address
A15, A14 Decoder
2
R/W:
Connected to Memory
R/W to control data
direction
Y0
Y1
Y2
Y3
8
A0-13
8
A0-13
16K RAM
Data
Address
CS
16K RAM
Data
Address
CS
16K RAM
Data
Address
CS
16K RAM
Data
Address
CS
Specific words are determined by the lower 14 address
lines connected to the memory device’s address inputs
14
Decoder Design Work Sheet
Internal Memory Address Lines
Address Bit:
000016
3FFF16
400016
7FFF16
800016
BFFF16
C00016
FFFF16
15 1413 1211 10 9
0 0 0 0 0 0 0
0 0 1 1 1 1 1
0 1 0 0 0 0 0
0 1 1 1 1 1 1
1 0 0 0 0 0 0
1 0 1 1 1 1 1
1 1 0 0 0 0 0
1 1 1 1 1 1 1
8
0
1
0
1
0
1
0
1
7
0
1
0
1
0
1
0
1
6
0
1
0
1
0
1
0
1
5
0
1
0
1
0
1
0
1
4
0
1
0
1
0
1
0
1
3
0
1
0
1
0
1
0
1
2
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
Bank0: A14=A15=0
Bank1: A15=0.A14=1
Bank2: A15=1.A14=0
Bank2: A15=1.A14=1
FIXED for each
bank
15
Comparators
• The basic function of a comparator is to
compare the magnitude of two binary quantities
to determine the relationship of those quantities.
• In its simplest form, a comparator circuit
determines whether two numbers are equal.
• A 1-bit comparator is implemented as:
UC1A
A
B
2
1
3
X
7433
X = 1 if A = B
16
•A complex comparator can be implemented taking into
account inequality. For two numbers A and B, we will have to
consider ( A = B, A < B, and A > B).
• The following figure gives a block diagram of a 4-bit
comparator:
A[3:0]
4
A>B
4-bit Comparator
A=B
A>B
B[3:0]
4
17
For the Output A > B to be active, we must have these conditions:
- If A3 = 1 and B3 = 0, (A3'B3) then A >B
- If A3 = B3 and A2 = 1(condition x3 for equality between A3 and
B3) and A2 = 1 and B2 = 0, (x3A2B2'), then A >B
etc
The 74X85 (X = LS, HC, or ALS) is a 4-bit comparator.
18
Encoders
• An n-input binary encoder is a logic circuit that,
given an n-bit input word X that contains one active
signal xi, generates and output word Z, which is a
binary representation of i, the index of the active
input signal.
• Thus an encoder is the inverse of a decoder, and
typically has n = 2k input lines of X and k output
lines for Z.
• A four-input encoder, for instance, has n = 4 and k =
2, and maps the input combinations 1000, 0100,
0010, and 0001 onto the output combinations 00, 01,
10, and 11 respectively.
19
A Binary Encoder
20
An encoder is intended to identify a single active input signal.
However there is nothing to prevent several of its X input lines
from being active at the same time, because they may be driven
from independent external sources.
To deal with this situation, most encoders are designed as priority
encoders, which have the property that when several inputs are
active at the same time, the output number I that appears on Z is
the index of the input line xi with the highest priority.
The following figures give the block diagram and logic equations
of a priority encoder.
21
Block Diagrams
Logic equations
22
ECNG 1014: Digital Electronics
Combinational Devices: Pt 2 Multiplexers
Section 5.7, Wakerly
23
A What?
A multiplexer (mux) is a device
that allows us to select one of nsets of b-bit data for transmission
to its b-bit output. It is a digital
switch.
24
E.g. 74151 8input x 1 bit MUX
74x151
EN_L
Select
Inputs
Data
Inputs
EN
A
B
C
D0
D1
D2
D3
D4
D5
D6
D7
If EN = 1
Then Y=0
Else
k = val(CBA)
Y=Dk
Endif
Y
Y
Y=ENmkDk, where mk is the k’th
minterm of select word CBA.
25
E.g.
2-input, 4-bit-wide 74x157
For I=1 to 4
If G=0
Then iY = 0
Else
If S=0
Then iY=iA
Else iY=iB
Endif
Endif
Endfor
74x157
G
S
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
iY = G(S’•iA + S • iB), i=12,3,4
26
As for decoders, can use MUXes to synthesise logic
E.g. Implement F=ab’+a’d+abc’ on a 2-1mux
Solution: With 2 inputs, D0 and D1, say, the MUX will have 1 select input,
SEL, say.
Step 1: Choose variables for direct connection to the select inputs. This
can be arbitrary but note that, as in all things, the actual choice will
affect the amount of work required to complete the design
Let SEL = a, say
Step 2: Using expression for F, which will be the MUX output, select
appropriate logic functions of remaining variables to drive the MUX
data inputs. This may be derived by comparison of the MUX expression
and the target logic function or from the function’s truth table
F= Y = SEL’D0 + SEL D1
=> F = D0 if SEL=0 OR F=D1 if SEL=1
<=> D0 = F|SEL=0
<=> D0 = F|a=0 = d
Similarly, D1 = F|a=1 = b’+bc’ =b’+c’
a
SEL
d
D0
b’+c’
D1
F
Y
27
E.g. Use a Kmap to realise F= WXZ’ + WX’Y + XZ on an 8-1 MUX.
Step 1: There will be 3 select inputs (why?) SEL0, SEL1, SEL2.
Let: W=SEL2, X=SEL1, Y=SEL0.
Step 2: From the K-map
determine each input as
YZ
D0 = 0
D1 = 0
a logic function of the
00 01 11 10
remaining variable (Z):
D2 = Z
00
0
0
0
0
01
0
1
1
0
11
1
1
1
1
WX
D6 = 1
D3 = Z
D7 = 1
D5 = 1
10
0
D4 = 0
0
1
1
e.g.: To determine the
function to be applied to
D3 note that D3 is
selected when
W=0, X=1, Y=1.
Now, identify all those
cells for which WXY=011.
Write the logic values in
these cells as a function
of the remaining variable,
Z.
28
On a 74151 …..
74x151
Note: No
logic gates
required!!
0
Y
X
W
0
0
Z
Z
0
1
1
1
EN
A
B
C
D0
D1
D2
D3
D4
D5
D6
D7
Y
Y
F= WXZ’ + WX’YZ + XZ
Exercise: Verify
that this works
by referring to
the operation of
the 74151 MUX
29
YZ
00 01 11 10
00
0
0
0
0
01
0
1
1
0
11
1
1
1
1
Same Function on a 4-1 MUX
WX
Y
10
0
0
1
1
Z
S0
S1
F
D0
D1
D2
D3
Y
30
Theorem on MUX realisations:
A 2n- to-1 MUX can be used to realise ALL (n+1)-variable logic
functions without the use of logic gates (save for inverters).
Proof:
A 2n- to-1 MUX will have n select lines. Take any n of the
variables, X0 - Xn-1, and connect them individually to these n
select lines (step 1!). For each of the 2n- select combinations, the
function value will depend only on the value of the last variable,
Xn (step 2!) and could therefore assume one of the 4 possible
functions of this one variable: 0, 1, Xn, Xn’. The function is
therefore realised by appropriately connecting any one these 4
functions of the last variable to the data inputs.
31
MUX uses
As a data selector (original purpose)
Not generally used for logic realisation using MSI
components but… used as the core of combinational
logic in some LSI and VLSI devices such as Field
Programmable Gate Arrays (FPGAs). FPGAs exploit
the MUX Theorem to allow general users to implement
logic functions at VLSI density at a very low cost.
32
Demultiplexers
• A demultiplexer basically reverses the
multiplexing function. It takes data from
one line and distributes them to given
number of output lines.
• A demultiplexer has N = 2k output lines, k
address selection and one data line. The
number of the output line active is specified
by the k bits address.
33
input
1 x 2n DEMUX
2n outputs
n-bit
selections
Demultiplexer
34
ECNG 1014: Digital Electronics
Combinational Devices: ROMs
35
Why “ROM”?
• Program storage
– Boot ROM for personal computers
– Complete application program storage for
embedded microprocessor systems.
• Actually, a ROM is a combinational circuit,
basically a truth-table lookup.
– Can perform any combinational logic function
– Address inputs
= function inputs
– Data outputs (stored data) = function outputs
36
ROM Internal Structure
• Internal array of (address) word and (data) bit lines
• Each intersection of word and bit lines interconnected by an element that can be
“programmed” to be open or short circuited
• Each word line is activated from the address via decoder
• Each bit line outputs a logic level corresponding to the state of the
interconnection with an activated word line
Memory
array
E.g. A ROM
Modern memories use MOS
transistors as interconnection
elements. In this example, a
fully connected transistor at
the intersection of an
activated word line and a bit
line results in a stored 0
(actually a 1 since the bit lines
are usually buffered via an
inverter to the corresponding
data output).
A disconnected transistor
results in a stored 1 (a 0 at
the output).
37
Two-dimensional decoding
• Accommodates large address widths in a more compact form
• Uses a decoder and MUX to select bits
2D decoding in a 2n x 1 ROM
A2
2n bits of
storage
An-1
A0
A1
S0
S1
Y
D0
38
Larger example, 32Kx8 ROM: Stack for word storage
215=32K address space
39
EPROMs, EEPROMs, Flash PROMs
• Programmable and erasable using floating-gate MOS transistors
• More reliable than fuse based PROMs
• Floating gate is isolated from rest of
circuit but can be charged/discharged
• When discharged, transistor can be
turned on by word line
• When charged transistor cannot be
turned on by word line
• EPROM: floating gate discharged via
UV light
• EEPROM/Flash PROMs: floating
gate can be discharged electrically
40
Typical commercial EPROMs
41
EEPROM programming
• Apply a higher voltage to force bit change
– E.g., VPP = 12 V
• Various bit erase procedures
– Byte-byte
– Entire chip (“flash”)
– One block (typically 32K - 66K bytes) at a time
• Programming and erasing are a lot slower than
reading (milliseconds vs. 10’s of nanoseconds)
42
Microprocessor EPROM application
Be cool!
43
Do NOT panic!
Full featrured
ROM structure
(except for
programming)
44
Logic-in-ROM
example:
2-4 Decoder with
polarity control
45
4x4 multiplier
example
Row Starting Address
XY
_0 _1 _2 _3 _4
Y
X
Data at Address Location
_5 _6 _7 _8 _9 _A _B _C _D _E _F
2*F16=2*1510
=3010=1E16
Hexadecimal
EPROM Listing
46
Exercise
Determine all the data words stored in the 8x4 PROM of figure 10-5, Wakerly
47
Exercise
Determine all the data words stored at A6-0= 0, 5, 29, 120 in the PROM of figure 10-7, Wakerly
48
ECNG 1014: Digital Electronics
Combinational Devices: PLDs
Wakerly Section 5.3
49
Programmable Logic Arrays (PLAs)
• Any combinational logic function can be realized
as a sum of products.
• Idea: Build a large AND-OR array with lots of
inputs and product terms, and programmable
connections.
– n inputs
• AND gates have 2n inputs -- true and complement of
each variable.
– m outputs, driven by large OR gates
• Each AND gate has a programmable connection to each
output’s OR gate.
– p AND gates where (p<<2n= no. minterms)
50
Example: 4x3 PLA, 6 product terms
AND
Array
OR
Array
Programming selectively breaks hardwired connections.
These are all fully committed at manufacture
51
Compact representation
• Actually, closer to
physical layout (“wired
logic”).
• In this model Default
output is a “1”. Must
programme “0’s”
52
Some product terms
I1’.I2’.I3’.I4’
I1’.I3.I4
53
PLA Electrical Design
Vcc
• See Section 5.3.5 -- wired-AND logic
Fuse
Default HIGH
Fuse intact => line can be
pulled low when xsistor ON
Fuse blown => line remains in
default HIGH state when
attempt to put xsistor ON
54
Programmable Array Logic (PALs)
• PLAs share product terms. How beneficial is product
sharing?
– Not enough to justify the amount of programmable
interconnections
• PALs ==> fixed OR array
– Each AND gate is permanently connected to a certain
OR gate.
• Example: PAL16L8
55
•
•
•
•
10 primary inputs
8 outputs, with 7 ANDs per output
1 AND for 3-state enable
6 outputs (IO1-6)available as
inputs
– more inputs, at expense of
outputs
– two-pass logic, helper terms
• Note inversion on outputs
– output is complement of sumof-products
– newer PALs have selectable
inversion
• EPROM as well as original OTP
(1-time programmable) versions
available
56
Designing with PALs
• Compare number of inputs and outputs of the
problem with available resources in the PAL.
• Write equations for each output using ABEL
or VHDL.
• Compile the program, determine whether
minimized equations fit in the available AND
terms.
• If no fit, try modifying equations or providing
“helper” terms.
57