Transcript CAD Challenges for Leading

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CAD Challenges for Leading-Edge
Multimedia Designs
Ira Chayut, Verification Architect
(opinions are my own and do not necessarily represent
the opinion of my employer)
Topics
Unique Requirements
Functional Verification
Synthesis
Physical Design
Manufacturability
Costs
Conclusions
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Unique Requirements
Short design cycles
Large international teams
Among the most complex and largest commercial creations
GPU
Gen1
Gen2
Gen3
Gen4
Gen5
Gen6
Technology
0.25u
0.18u
0.15u
0.13u
0.11u
90nm
1 - dual edge clocking
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Placeable
Transistors Frequency Instances
9M
125MHz
1M
1
25M
250MHz
1.5M
1
57M
350MHz
3M
1
130M
450MHz
5.5M
1
222M
525MHz
12M
302M
700MHz 1
16M
Flops
~60K
~200K
~500K
~750K
~1.2M
~1.6M
Models
C vs V
90K/300K
100K/300K
400K/800K
700K/1.3M
1M/1.6M
1.2M/1.9M
Directed
Arch
GDS2
Tests File size
300
800KB
6000
2GB
25000
4.5GB
50000
8GB
90000
16GB
100000 19GB
Example: PS3 Graphics Chip
More than 300M transistors
About the same as the sum all of the following:
XBOX GPU (60M)
PS2 Graphics Synthesizer (43M)
Game Cube Flipper (51M)
Game Cube Gekko (21M)
XBOX Pentium3 CPU (9M)
PS2 Emotion Engine (10.5M)
Athlon FX 55 (105.9M)
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Each Generation Demands More
Copyright © NVIDIA Corporation 2005
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Looking Into the Crystal Ball
Features are set by the
software industry
leaders – we have to
guess when new
features will be required
by the market
Shorter development
cycles decrease the
fuzziness in our
predictions
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The Family Grows Quickly
Time matters - each new flagship product must be
followed by derivatives – almost concurrently
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Design Flow
External
Reqmnts
Architecture &
Algorithms
Class
Definitions
Foundry
Data
Microarchitecture
Speed/PWR/Area
Requirements
Data Path / STD Cell
C-models
RTL
Drivers
Validation
Simulation
Logic
Verification
Floor Plan
Custom
cells
Emulation
Architecture
ASIC
Physical Design
Software
Marketing
Operations
Sales
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Test Insertion
Place&Route;
Timing Optimize;
Data Path
TapeOut
Physical
Verification
Test
Reqmnts
Foundry
Reqmnts
Size Matters
We are quickly approaching 1 Billion transistors
with high logic-to-memory ratios
The complexity of our designs is growing faster
than the number of transistors
All aspects of chip design affected, including:
Verification, Synthesis, Physical Design, and
Manufacturability
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Complexity Increases Exponentially
Chip component count
increases exponentially
over time (Moore’s law)
Transistors per chip
1600
Millions of transistors
1400
Interactions increase
super-exponentially
1200
1000
IP reuse and parallel
design teams mean
more functions per chip
800
600
400
200
0
1995
2000
2005
Year
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2010
2015
Verification gets
combinatorially
more difficult
Functional Verification
Speed matters – Multimedia designs have a large
pool of legacy tests, many of which are long
running
Multiple vendor CAD tools must inter-operate
smoothly
Verification now limits what features make it to
silicon
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Why Verification is Unable to Keep Up
Verification effort gets combinatorially more
difficult as functions are added
BUT
Verification staffing/time cannot be made
combinatorially larger to compensate
AND
Chip lifetimes are short, which decreases the time
available for verification
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Emulation – Necessary and Costly
$100 Million
worth of
emulators
.... and
growing
Multiple
boxes
needed for
a single
chip
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Synthesis
Synthesize early and synthesize often – CAD tools
must support early synthesis to provide area,
timing, and power estimates
Must have better correlation between logic
synthesis and post-layout results
Early synthesis and layout can change the
architecture and the design – this is only possible
if problems are caught early in the design cycle
ECO support is growing in importance
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Physical Design
Deep submicron designs pose new problems for
timing, power, and signal integrity
Leading-edge multimedia designs are so large that
we have to decompose the problem into partitions
The number of partitions is growing and the size of
chips (in clock cycles) is increasing
Timing budgeting across partitions can be very
wasteful – CAD tools must be able to work
across partitions (at least “skin deep”)
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ECO support is growing in importance
Holistic Approach
CAD tools and flow must consider power, area, and
timing throughout the design process
Information from each tool must be able to fed
back and forward to other tools in the flow
Each chip must be able to choose the best
vendor’s tool for each step
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Manufacturability
Deep submicron technologies are much more
affected by tiny variations between dies – CAD
tools need to help increase yields by designing in
margins (realizing that there are tradeoffs between
these margins and size/speed)
At-speed wafer testing of enormous chips require
on-chip support – CAD tools must make this
automatic and painless with minimal
silicon cost
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Money Matters
The costs of CAD tools and R&D staff are growing
faster than the Multimedia TAM
CAD tools must decrease their cost-per-seat
CAD tools must make each engineer more
productive over the entire design cycle
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Conclusions
Size matters
Performance matters
Inter-operability matters
Holistic view matters
Money matters
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