Transcript Document

NUMERICAL TECHNOLOGIES, INC.
Assessing Technology
tradeoffs for 65nm logic
circuits
D Pramanik, M Cote, K Beaudette
Numerical Technologies Inc
Valery Axelrad
Sequoia Design Systems
INTRODUCTION
 At the 65nm node interaction between process



and design can lead to manufacturability crisis
Methodology for assessing tradeoffs between
device, circuit and process limits
Use simulation tools to investigate different
scenarios for optimum tradeoffs
Electrical and Physical simulations
NUMERICAL TECHNOLOGIES, INC.
SPIE 2003 2/27/03
Technology variants
 Every Technology node has variants to address



different market segment needs
Transistors with different parameters are
offered based on application needs
Device specifications should drive
manufacturability requirements that impact
overall costs
One size does not fit all !!
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High Volume Market segments
 Low Power (Cellphones/PDA)
 Low operating voltage(<1V)
 Low operating frequency (<200MHz)
 High density
 Low active and standby current
 Low cost
 High Performance (PC/Server/Graphics )
 Nominal operating voltage
 High operating frequency (>2GHz)
 High density
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Technology Elements
Row
Cell
Block
Chip
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MOSFET
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Design flow
Architectural Design
Design rules
Device Models
Device Simulation
OPC
Phase Shifting
Functional specs
Silicon Simulation
RTL design
SubW
Libs.
Silicon
Silicon Verification
Verification
Synthesis
Floorplanning
Place and route
LVS, DRC, Extract
OPC
Phase Shifting
Silicon Verification
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Final
Analysis &
Verification
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Key formulas
Device
 Ion = vsatW Cox(Vdd - Vdsat)
Vdsat when L

Ioff = 10 -6exp(-Vth/S) where S= 80mV/decade
Circuit
Delay
time = ClVdd/Ion; Cl - avg load capacitance
Dynamic power = nCl Vdd2f
 Vdd - Supply Voltage
n - avg number of switching events
 L - Gate length
 W - Gate width
 Lithography
 Cox- Gate capacitance
 Min Pitch = k1l/NA
 Vth - Threshold voltage
2
 DOF = k2l/NA
 Ion - Fully on current
 Ioff - Off state current
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Device simulation
Electrical Parameters
L
Gate
Spacer
xj
tox
Source
Drain
 Vdd - Supply Voltage
 L - Gate length
 W - Gate width
 tox- Oxide thickness
 xj – Junction depth
 Ion - Fully on current
 Ioff - Off state current
Transistor cross-section
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Device currents vs L
Type
High
Performance
Low Power
Vdd
(V)
L
Ion
Ioff
(nm)
(ma/mm)
(A/mm)
0.9
20
-
Short
30
0.91
37E-9
34
0.74
3E-9
40
0.6
3E-10
25
-
Short
60
0.42
6E-11
65
0.385
3E-11
70
0.354
2E-11
0.9
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Device Characteristics
1.E-04
1.E-05
Ion vs Ioff characteristics for
device technology
Ioff(A/um)
1.E-06
1.E-07
1.E-08
1.E-09
Lo Pwr
1.E-10
Hi Perf
1.E-11
Gate oxide
Lo Pwr - 16A
Hi Perf - 13A
1.E-12
0
200
400
600
Ion(ma/um)
800
1000
1.E-04
Hi Perf
1.E-05
1.E-06
Ioff (A/ m m)
Off state leakage vs
Gate length for both
device technologies
Lo Pwr
1.E-07
1.E-08
1.E-09
1.E-10
1.E-11
1.E-12
0
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0.02
0.04
0.06
0.08
L ((mm)
0.1
0.12
0.14
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Electrical criteria
65nm
Active
Aerial Image contours overlaid on drawn features
showing CD variation along length of gate.
CD at listed sites shown in table.
Avg CD (excluding 4) = 61nm
#
CD
(nm)
1
2
3
65
60
54
4
5
6
7
8
33
70
55
61
62
Use OPC to bring avg CD back to 65nm
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Cell generation
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Technology file -process
design rules and
recommended rules
Define architecture (cell
height, power rails etc)
Input circuit netlist
Cell placed, routed and
compacted
View completed cell and
if necessary modify,
layout and re-compact
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Same function ;Different Drive
And 2X0
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And 2X4
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Cell placement & Circuit Timing
tg
ti
A
B
Timing delay between A and B is the sum of delays through individual
cells(tg) and across interconnects (ti)
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Lithography choices with 193nm
Layout
Att PSM
NA 0.85 OAI
Strong Phase shift
Best contrast and DOF with Strong Phase shift
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FullPhase layer generation
Original Active and Poly layers
Phase shift layers
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Trim layer
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Aerial Image using 193nm
NA = 0.75; sigma=0.4; dose = 1X
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NA = 0.75; sigma=0.4; dose = 3X
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Manufacturability analysis
Analysis of simulated images show following areas of
improvement
 Process


Improved Depth of Focus (DOF) by changing poly pitch from
160nm to 180nm
Better CD control - less OPC
 Electrical
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Poly contact pads shrink substantially leading to high contact
resistance.
Poly-contact overlap improved by going to larger contacts
and larger poly extensions
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Impact of Design rules
Poly pitch – 160nm
Contacts – 80nm
Contact extension – 35nm
Poly pitch – 180nm
Contacts – 90nm
Contact extension – 45nm
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Simulation of new cells
Defocus 0nm
Cell with larger poly pitch
and larger contact pads
Defocus 100nm
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Summary
 Simulation of device characteristics allow the


circuit impact of lithography variations to be
assessed
Strong Alt PSM needed for printing poly
features using 193nm
Automated layout tools allow tradeoff between
layout design rules , circuit density and
manufacturability
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