Transcript Gate Delay Modeling Part-1

Logic Gate Delay Modeling -1
Bishnu Prasad Das
Research Scholar
CEDT, IISc, Bangalore
[email protected]
OUTLINE
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Motivation
Delay Model History
Delay Definition
Types of Models
-RC delay Models
-Logical Effort
• Limitation of Logical Effort
• Summary
Motivation
• Why Model is required?
–
–
–
–
For fast simulation
Solving differential equation is difficult
For creating optimal design
Real design will be always more costly and
time consuming.So model is used to simulate
the system before actual implementation.
Types of Models
• Physical Models
– Based on Physical phenomena of device
• Empirical Models
– Based on curve fitting ( i.e. Quadratic,Cubic etc.)
– No physical significance.
• Table Models
– Storing the data in a Lookup Table
– Do interpolation between stored data
Delay Model History
Courtesy : Synopsys
Delay Definitions
• tpdr: rising propagation delay
– From input to rising output crossing VDD/2
• tpdf: falling propagation delay
– From input to falling output crossing VDD/2
• tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
• tr: rise slew
– From output crossing 0.2 VDD to 0.8 VDD
• tf: fall slew
– From output crossing 0.8 VDD to 0.2 VDD
Delay Definitions
• tcdr: rising contamination delay
– From input to rising output crossing VDD/2
• tcdf: falling contamination delay
– From input to falling output crossing VDD/2
• tcd: average contamination delay
– tpd = (tcdr + tcdf)/2
Delay Definitions
• tpdr: rising propagation delay
– From input to rising output crossing VDD/2
• tpdf: falling propagation delay
– From input to falling output crossing VDD/2
• tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
• tr: rise time
– From output crossing 0.2 VDD to 0.8 VDD
• tf: fall time
– From output crossing 0.8 VDD to 0.2 VDD
Delay Definitions
• tcdr: rising contamination delay
– From input to rising output crossing VDD/2
• tcdf: falling contamination delay
– From input to falling output crossing VDD/2
• tcd: average contamination delay
– tpd = (tcdr + tcdf)/2
RC Delay Models
• Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely proportional to width
d
g
d
k
s
s
kC
R/k
kC
2R/k
g
g
kC
kC
s
d
k
s
kC
g
kC
d
Example: 3-input NAND
• Sketch a 3-input NAND with transistor
widths chosen to achieve effective rise and
fall resistances equal to a unit inverter (R).
Example: 3-input NAND
• Sketch a 3-input NAND with transistor
widths chosen to achieve effective rise and
fall resistances equal to a unit inverter (R).
Example: 3-input NAND
• Sketch a 3-input NAND with transistor
widths chosen to achieve effective rise and
fall resistances equal to a unit inverter (R).
2
2
2
3
3
3
3-input NAND Caps
• Annotate the 3-input NAND gate with gate
and diffusion capacitance.
2
2
2
3
3
3
3-input NAND Caps
• Annotate the 3-input NAND gate with gate
and diffusion capacitance.
2C
2
2C
2C
2C
2
2C
2C
2
2C
3C
3C
3C
2C
2C
3
3
3
3C
3C
3C
3C
3-input NAND Caps
• Annotate the 3-input NAND gate with gate
and diffusion capacitance.
2
2
2
3
5C
5C
5C
3
3
9C
3C
3C
Elmore Delay
• ON transistors look like resistors
• Pullup or pulldown network modeled as RC ladder
• Elmore delay of RC ladder
t pd 

Ri to  sourceCi
nodes i
 R1C1   R1  R2  C2  ...   R1  R2  ...  RN  C N
R1
R2
R3
C1
C2
RN
C3
CN
Example: 2-input NAND
• Estimate worst-case rising and falling delay
of 2-input NAND driving h identical gates.
2
2
A
2
B
2x
6C
2C
Y
4hC
h copies
Example: 2-input NAND
• Estimate worst-case rising and falling delay
of 2-input NAND driving h identical gates.
2
2
A
2
B
2x
6C
Y
4hC
2C
R
Y
(6+4h)C
t pdr 
h copies
Example: 2-input NAND
• Estimate rising and falling propagation delays
of a 2-input NAND driving h identical gates.
2
2
A
2
B
2x
6C
Y
4hC
2C
h copies
R
Y
(6+4h)C
t pdr   6  4h  RC
Example: 2-input NAND
• Estimate rising and falling propagation delays of a
2-input NAND driving h identical gates.
2
2
A
2
B
2x
6C
2C
Y
4hC
h copies
Example: 2-input NAND
• Estimate rising and falling propagation delays of a
2-input NAND driving h identical gates.
2
2
A
2
B
2x
x
R/2
R/2
2C
6C
Y
(6+4h)C
Y
4hC
2C
h copies
t pdf 
Example: 2-input NAND
• Estimate rising and falling propagation delays of a
2-input NAND driving h identical gates.
2
2
A
2
B
2x
x
R/2
R/2
2C
Y
(6+4h)C
6C
Y
4hC
h copies
2C
t pdf   2C   R2    6  4h  C   R2  R2 
  7  4h  RC
Delay Components
• Delay has two parts
– Parasitic delay
• 6 or 7 RC
• Independent of load
– Effort delay
• 4h RC
• Proportional to load capacitance
Contamination Delay
• Best-case (contamination) delay can be substantially
less than propagation delay.
• Ex: If both inputs fall simultaneously
2
2
A
2
B
2x
R R
Y
(6+4h)C
6C
Y
4hC
2C
tcdr   3  2h  RC
Layout Comparison
• Which layout is better?
VDD
A
VDD
B
Y
GND
A
B
Y
GND
Delay in a Logic Gate
• Express delays in process-independent unit
d
d abs

• Delay has two components
d f p
• f is due to external loading
• p is due to self loading
τ = 3RC
= FO1 delay without
parasitic delay
Delay in a Logic Gate
• Express delays in process-independent unit
d
d abs

• Delay has two components
τ = 3RC
= FO1 delay without
parasitic delay
d f p
• Effort delay f = gh (a.k.a. stage effort)
– Again has two components
Delay in a Logic Gate
• Express delays in process-independent unit
d
d abs

• Delay has two components
τ = 3RC
= FO1 delay without
parasitic delay
d f p
• Effort delay f = gh (a.k.a. stage effort)
– Again has two components
• g: logical effort
– Measures relative ability of gate to deliver current
– g  1 for inverter
Delay in a Logic Gate
• Express delays in process-independent unit
d
d abs

• Delay has two components
τ = 3RC
= FO1 delay without
parasitic delay
d f p
• Effort delay f = gh (a.k.a. stage effort)
– Again has two components
• h: electrical effort = Cout / Cin
– Ratio of output to input capacitance
– Sometimes called fanout
Delay in a Logic Gate
• Express delays in process-independent unit
d
d abs

• Delay has two components
τ = 3RC
= FO1 delay without
parasitic delay
d f p
• Parasitic delay p
– Represents delay of gate driving no load
– Set by internal parasitic capacitance
Effort Delay
• Logical Effort g
= Cingate/Cin_unit_inv
• Electrical Effort h
= Cout / Cingate
• f
= g*h = (Cingate/Cin_unit_inv)*(Cout / Cingate)
= (Cout / Cin_unit_inv)
• (Dactual)ext = g*h * τ = (Cout / Cin_unit_inv)*3*R*C
= (Cout / Cin_unit_inv)*R*Cin_unit_inv
= Cout*R
Computing Logical Effort
• DEF: Logical effort is the ratio of the input
capacitance of a gate to the input capacitance of
an inverter delivering the same output current.
• Measure from delay vs. fanout plots
• Or estimate by counting transistor widths
2
Y
2
A
2
Y
1
Cin = 3
g = 3/3
A
2
B
2
Cin = 4
g = 4/3
A
4
B
4
Y
1
Cin = 5
g = 5/3
1
Catalog of Gates
• Logical effort of common gates
Gate type
1
1
Inverter
NAND
NOR
Tristate / mux 2
XOR, XNOR
2
Number of inputs
3
4
n
4/3
5/3
2
4, 4
5/3
7/3
2
6, 12, 6
6/3
(n+2)/3
9/3
(2n+1)/3
2
2
8, 16, 16, 8
Catalog of Gates
• Parasitic delay of common gates
– In multiples of pinv (1)
Gate type
Inverter
NAND
NOR
Tristate / mux
XOR, XNOR
1
1
2
Number of inputs
2
3
4
n
2
2
4
4
3
3
6
6
4
4
8
8
n
n
2n
Delay Plots
= gh + p
6
NormalizedDelay:d
d =f+p
2-input
NAND
Inverter
g=
p=
d=
5
g=
p=
d=
4
3
2
1
0
0
1
2
3
4
ElectricalEffort:
h = Cout / Cin
5
Delay Plots
= gh + p
• What about
NOR2?
6
NormalizedDelay:d
d =f+p
2-input
NAND
Inverter
5
3
g=1
p=1
d = h +1
2
EffortDelay:f
4
g = 4/3
p=2
d = (4/3)h + 2
1
Parasitic Delay: p
0
0
1
2
3
4
ElectricalEffort:
h = Cout / Cin
5
Example: Ring Oscillator
• Estimate the frequency of an N-stage ring
oscillator
Logical Effort: g =
Electrical Effort: h =
Parasitic Delay: p =
Stage Delay:
d=
Frequency:
fosc =
Example: Ring Oscillator
• Estimate the frequency of an N-stage ring
oscillator
Logical Effort: g = 1
Electrical Effort: h = 1
Parasitic Delay: p = 1
Stage Delay:
d=2
Frequency:
fosc = 1/(2*N*d) = 1/4N
Example: FO4 Inverter
• Estimate the delay of a fanout-of-4 (FO4) inverter
d
Logical Effort: g =
Electrical Effort:h =
Parasitic Delay: p =
Stage Delay:
d=
Example: FO4 Inverter
• Estimate the delay of a fanout-of-4 (FO4) inverter
d
Logical Effort: g = 1
Electrical Effort: h = 4
Parasitic Delay: p = 1
Stage Delay:
d=5
The FO4 delay is about
200 ps in 0.6 mm process
60 ps in a 180 nm process
f/3 ns in an f mm process
Multistage Logic Networks
10
g1 = 1
h1 = x/10
x
g2 = 5/3
h2 = y/x
y
g3 = 4/3
h3 = z/y
z
g4 = 1
h4 = 20/z
20
Limits of Logical Effort
• Chicken and egg problem
– Need path to compute G
– But don’t know number of stages without G
• Simplistic delay model
– Neglects input rise time effects
• Interconnect
– Iteration required in designs with wire
• Maximum speed only
– Not minimum area/power for constrained delay
Summary
RC Delay Model
Delay measurement using Logical Effort Method
Gate sizing using Logical Effort for minimum
delay
Limitations of Logical Effort
Reference
• N. H. E. Weste and D. Harris, “CMOS VLSI Design, A
circuits and Systems Perspective” 3rd edition Pearson
Addison Wesley
• Rabaey, Chandrakasan and Nikolic, “Digital Integrated
Circuits, a Design Perspective”, Pearson Education