Transcript Designing a Low Power SRAM for PICo

“I LOVE VLSI” ~Benton Calhoun, August 25th 2009
DESIGNING A LOW POWER
SRAM FOR PICO
ECE4332 : Team 4
Sharif Morad, Maxwell Martin, Jaleesa Boykin,
Marc Hall
December 2nd 2009
DESIGN GOALS

Main metric for low power 1Mb SRAM:


(Total Power)2 * Delay * Area = (mW2*ns*mm2)
Requirements:
32 bit word size for read or write
 Inputs: Address bits, data in, read, write, CLK
 Outputs: data out
 Functionality at all process corners with various
temperatures

ARRAY ARCHITECTURE

16 blocks


8 words/block
256 x 256 bit cells
per block

Block Pre-charging

Hierarchical WL

Shorted BLs/BLBs

Sense Amps
BIT CELL
6 xtor bitcell
 Calculations and vigorous testing to minimize
width

DECODERS

Block SelectHierarchical WLs


Saves Power and Delay
Decoder Enable Select

Saves Power
DATA ACCESS

Shorting BL/BLB


Saves area
MUXing only column blocks saves 32256 xtors
SENSE AMPLIFIER

32 Sense Amps/block
column


Shorted BL/BLB



Reduce Power
Saves area
Saves 35712 xtors
Delayed SE signal
to wait for BL/BLB
data
PRE-CHARGE BLOCK

BL/BLB shorted


Saves Area


Only require 4 precharge blocks as
opposed to 16
6144 xtors
Hierarchical pre-charge



Block Select Signal
Saves Power
Reduces CLK signal
load
DATA WRITING

Shorting BL/BLB


Data xtors for only
block column


Saves Area
Saves 6144 xtors
Column Block
Selector

Saves power
FURTHER OPTIMIZATIONS

Lower VDD




5V to 2.5V
Reduce Clock period
Reduce ratio width of pre-charge transistors to
data write transistors
Clock signal buffering

Used FO4
LAYOUT


Used past designs
Utilized methods to
save area
Mirroring
 Minimum sized gaps

SIMULATION

Simulated model of entire array

Extracted bit line and word line R/C


based on layout lengths/widths
Tested and verified functionality at
Process corners (TT, FF, SS, SF, FS)
 Different voltages (2.5V, 5V, 5.5V, 4.5V)
 Temperature (50C, 27C, 0C)

RESULTS
Write 1, Read 1, Write 0 at TT, 2.5V (nominal), 27°C
METRICS

Average Power:


Delay:


72.18ns (worst case delay for read)
Total Area:


~68.916mW
Approximately .524mm2
Power Metric: 179633.89 (mW2*ns*mm2)
CHALLENGES

Tradeoff decisions


Which knobs to turn and amount of sensitivity
Wiring/Layout
Took a long time, changing design was difficult
 SKILL may have helped
 Magnitude of SRAM


Simulation


Troubleshooting Cadence
Sticking to schedule/time constraints

Server crash
QUESTIONS?