Transcript leakage-vlsi2002-slides

Symposium on VLSI Circuits 2002
Leakage-Biased Domino
Circuits for Dynamic FineGrain Leakage Reduction
Seongmoo Heo and Krste Asanović
Massachusetts Institute of Technology
Lab for Computer Science
Leakage Power
• Growing impact of leakage power
– Increase of leakage power due to
scaling of transistor lengths and
threshold voltages
– Power budget limits use of fast leaky
transistors
• Challenge:
– How to maintain performance scaling in
face of increasing leakage power?
Leakage Reduction Techniques
Static: Design-time Selection of Slow
Transistors (SSST) for non-critical paths
– Replace fast transistors with slow ones on
non-critical paths
– Tradeoff between delay and leakage power
Dynamic: Run-time Deactivation of Fast
Transistors (DDFT) for critical paths
– DDFT switches critical path transistors
between inactive and active modes
Observation:
Critical paths dominate leakage after
applying SSST techniques
Example: PowerPC 750
– 5% of transistor width is low Vt, but
these account for >50% of total leakage.
DDFT could give large leakage
savings
DDFT Techniques for Domino
• Dual-Vt Domino [Kao and Chandrakasan, 2000]
– High Vt for precharge phase
– Input gating  increased delay and active
energy
– High Vt keeper  increased noise margin
1
(High Vt transistor: Green colored)
DDFT Techniques for Domino
• Dual-Vt Domino
– High Vt for precharge phase
– Input gating  increased delay and active
energy
– High Vt keeper  increased noise margin
1
DDFT Techniques for Domino
• MHS-Domino [Allam, Anis, Elmasry, 2000]
– Clock-delayed keeper
sleepb
clk
in
DDFT Techniques for Domino
• MHS-Domino
– Pull-down through PMOS  short circuitcurrent in static inverter
sleepb=0
clk
in
dynamic node
Conventional Domino
clk
in
Leakage-Biased (LB) Domino
Two sleep transistors in non-critical path
Sleep
clk
in
Sleepb
Leakage-Biased (LB) Domino
Active mode
Sleep(=0)
clk
in
Sleepb(=1)
Leakage-Biased (LB) Domino
Sleep mode
Sleep(=1)
clk(=1)
In(=0)
NODE1 (10)
Sleepb(=0)
LB-Domino biases itself into a low-leakage
stage by its leakage current
NODE2
(01)
Han-Carlson Adder
• Evaluation with carry generation
circuit of a 32-bit Han-Carlson adder
– 6 levels of alternating dynamic and
static logic
– 4 circuits: LVT, DVT, LB, and LB2
• Constraints
– Input/Output noise margin kept to 10%
of Vdd
– Precharge/Evaluation delay equalized to
within 1% error
PG Cells of Han-Carlson Adder
(a) Low Vt (LVT)
(c) Leakage-Biased 1 (LB)
(b) Dual Vt (DVT)
(d) Leakage-Biased 2 (LB2)
Processes
• 180nm: TSMC 180nm Processes
• 70nm: BPTM 70nm Processes
Process
High Vt
(NMOS/PMOS)
180nm
70nm
0.46V/-0.45V 0.39V/-0.40V
Low Vt
(NMOS/PMOS)
Vdd
0.27V/-0.23V 0.15V/-0.18V
Temperature
1.8V
0.9V
100C
100C
Input Vectors
• 3 different input vectors
– Active energy and leakage power dependent
upon inputs
– Vec1 discharges no dynamic nodes
– Vec2 discharge half of dynamic nodes
– Vec3 discharge all dynamic nodes
Vector 1
Vector 2
Vector 3
A
B
Ci
0x00000000 0x00000000 0
0xffffffff
0xffffffff
0x00000000
0xffffffff
0
1
Delay and Active Power: 180nm
Eval/Prech delay
Delay (ps)
200
eval
prech
Energy (nJ)
240
Active energy
160
120
80
40
0
LVT DVT LB LB2
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
vec1
vec2
vec3
LVT DVT LB LB2
Delay and Active Power: 70nm
Eval/Prech delay
Delay (ps)
50
35
eval
prech
30
Energy (pJ)
60
Active energy
40
30
20
25
20
15
10
10
5
0
0
LVT DVT LB LB2
vec1
vec2
vec3
LVT
DVT
LB
LB2
Steady-State Leakage Power
120
vec1
vec2
vec3
100
80
60
40
20
0
LVT DVT
LB
LB2
70 nm process
Leakage power (uW)
Leakage power (uW)
180 nm process
10000
1000
vec1
vec2
vec3
100
10
1
LVT DVT LB LB2
Cumulative Sleep Energy: 180nm
vec1
250
250
250
Energy (pJ)
vec3
vec2
200
200
200
150
150
150
100
100
100
50
50
50
0
0
0
0
1
2
Time (us)
3
0
1
2
Time (us)
3
LVT
DVT
LB
LB2
0
1
2
Time (us)
3
Cumulative Sleep Energy: 70nm
vec1
20
20
Energy (pJ)
vec3
vec2
20
16
16
16
12
12
12
8
8
8
4
4
4
0
0
0
0
5
10
Time (ns)
0
5
Time (ns)
10
LVT
DVT
LB
LB2
0
5
10
Time (ns)
Conclusion
• Leakage-Biased Idea
– Leakage can be used to bias nodes into
low-leakage states
• LB-Domino for Fine-grain leakage
reduction
– 100x reduction in steady-state leakage
– Low deactivation and wakeup time
– Low transition energy
• >10ns breakeven time at 70nm process
Acknowledgement
• Funded by DARPA PAC/C award F3060200-2-0562, NSF CAREER award CCR0093354, and a donation from Infineon
Technologies.