Transcript Structured Logic design With VHDL

EEET0441
HDL CHIP DESIGN
EEET0441Course Description
Theory
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Introduction to
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Digital system design
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ASIC design technology
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FPGA design technology
Practices
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Languages
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For software
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For Hardware
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Fore Hardware and Software
Language Fundamental:
Verilog
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RTL/Gate level system design
examples
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Combinational and Sequential design
examples
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Finite state machine design examples
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Design Tools (Xilinx ISE) and
demonstrations for RTL/Gate Level
Transistor/Layout level system
design examples
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MOS revisit
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Static CMOS combinational circuit
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Design Tools (MicroWind) and
demonstrations for Transistor/Layout
Level
Others
Books
 1.The Verilog Hardware Description Language, 5th Ed., Donald
E.Thomas, Philip R. Moorby, Kluwer Academic Publisher, 2002
2. Hdl Chip Design: A Practical Guide for Designing, Synthesizing &
Simulating Asics & Fpgas Using Vhdl or Verilog, Douglas J. Smith,
Doone Publications, September 1996
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3.การออกแบบระบบดิจิตอลด้วยภาษา HDL (HDL for digital system
designs, ตาราเรียน, ธีรยศ เวียงทอง, มหาวิทยาลัยเทคโนโลยีมหานคร,
2552
Contacts
Theerayod Wiangtong
Electronic Department
Room: A502
Email: [email protected]
Website: www.ee.mut.ac.th/home/theerayod
HDL INTRODUCTION
Modern chip design aspects
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Modern chips became too complex
The number of transistors in a modern chip is over a
100 M
Transistor count per chip and chip speed rise up to
50% per year
Estimated time needed for manual implementation
(100 M transistor, 10 sec/transistor) – 135.5 years!!!
Modern ASIC design approach
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ASIC – Application Specific Integrated Circuit
Modeling system should be designed and described
in the highest abstraction level possible
Simulation and testing at high abstraction level
Conversion of the modeled system
into the low abstraction level model (gate, circuit, silicon level)
using sophisticated synthesis tools
Key point – CAD (Computer Aided Design)
Modern ASIC design approach
Design
RTL Model
Description
Simulation & Testing
HIGH ABSTRACTION LEVEL
Conversion
LOW ABSTRACTION LEVEL
Gate Level Model
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Transistor Level
Model
HDLs (Hardware Description Languages)
are used for system description at the high abstraction level
Verilog vs VHDL
VHDL
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VHDL - VHSIC Hardware Description Language
VHSIC - Very High Speed Integrated Circuit
Development of VHDL began in 1983, sponsored by
Department of defense, further developed by the
IEEE and released as IEEE Standard 1076 in 1987
Today it is De facto industry standard for hardware
description languages
The abstraction hierarchy
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The abstraction hierarchy can be expressed in two domains:
structural domain, behavioral domain
Structural domain – component model is described
in terms of an interconnection of more primitive components
Behavioral domain – component model is described
by defining its input/output response
VHDL is used for both structural and behavioral description
Six abstraction hierarchy levels of detail commonly used in
design: silicon, circuit, gate, register, chip and system
Design Synthesis
(1) Natural language synthesis Transformation from
English to an algorithmic representation
(2) Algorithmic synthesis Translation from an
algorithmic representation to a data flow
representation
(3) Logic synthesis Translation from data flow
representation to a structural logic gate
representation
(4) Layout synthesisTranslation from logic gate to
layout and circuit representation
Design Tools
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Editors – textual (circuit level – SPICE gate, register, chip –
VHDL) or graphic (used at all levels)
Simulators – stochastic (system level)
or deterministic (all levels above the silicon level)
Checkers and Analyzers – employed at all levels, used for
example
(1) to insure that the circuit layout can be fabricated reliably
(rule checkers),
(2) to check for the longest path through a logic circuit or
system (timing analyzers)
Synthesizers and Optimizers – improving a form
of the design representation
BASIC FEATURES OF VHDL
Design entities
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In VHDL a logic circuit is represented as a design entity
A design entity consists of two different VHDL types of
description:
(1) Interface description (reserved word is entity)
(2) One or more architectural bodies (reserved word is
architecture)
entity D_FF
D
Q
defining D FF interface (ports)
D FF
CLK
R
architecture of D_FF
specifying the behavior of the entity
Designed digital device
VHDL representation
Entity
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The entity part provides system’s interface specification
as seen from the outside and is generally comprised of:
(1) Parameters (such as bus width or max clock
frequency)
(2) Connections (system input and output ports)
entity DesignEntityName is
-- parameters
…
-- connections
port (ports);
end entity DesignEntityName;
Architectural bodies
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Architectural bodies are specifying the behavior of the entity
architecture ArchitectureName of DesignEntityName is
-- signal declarations
begin
-- concurrent statements
end architecture ArchitectureName;
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There are two types of architectural bodies: algorithmic,
structural
Algorithmic - at the beginning of the design process,
designers usually would like to check the accuracy of the
algorithm without specifying the detailed implementation
Structural - the logic design stage, detailed implementation,
entity as a set of interrelated components
Summary
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Why HDL?
 HDL
in logic level synthesis
 HDL in transistor level synthesis
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VHDL revisit
Design process
Questions?