Transcript 無投影片標題 - CUHK Electronic Engineering Programme

Semiconductor Technology Challenges
- A Foundry Perspective
Frank Wen, Ph.D.
Executive Board Director
and President
International Technology
Conference, HK, 2002
Date : 01. 14, 2003
地點 :
Agenda:

UMC Technology Roadmap.

300mm Fab.

Technology Challenges.

Summary.
Brief Outline:
In this presentation we start with UMC’s technology roadmap as an example to
elaborate the nano-meter semiconductor technology progresses in reference to
the ITRS technology roadmap. Then we cover the recent progress in the 300mm
Fab and technology at UMC. Some analysis on 300mm wafer advantages and its
implications are also presented.
Technology challenges for both FEOL and BEOL processes are discussed. It
encompasses photolithography advancement, device structures and interconnect
technologies like copper/low-K dielectric material. In addition, some specialty
devices and materials utilized in the advanced device applications, e.g. strained
silicon and SOI technologies, are also illustrated.
Finally a brief summary of technology challenges and future trend for joint
technology development with IDM’s outsourcing strategy are also discussed.
UMC Technology Roadmap
UMC Leads SIA Roadmap
2000
2001
2002
2003
2004
2005
2006
2007
Low-k (k=2.7)
LOGIC
ITRS
0.15um
0.13um
Al,Cu
Cu
0.13um
90nm
Cu
65nm
Cu
90nm
Box center represents pilot production start schedule.
Box center marks the start of pilot production.
65nm
Fundamental Challenges - Rising Fab Cost
$3,600M
US$ millions
3,500
$3,000M
3,000
2,500
$1,750M
2,000
$1,250M
1,500
1,000
500
0
$700M
$400M
$200M $300M
1983
1987
1990
1994
1997
1999
2001
2003
wafer
4"/5" 5"/6"
6"
6"/8"
8"
8"
12"
12"
process 1.2um 1.0um 0.8um 0.5um 0.35um 0.25um 0.13um 0.09um
* Source : Dataquest, UMC
Fab 12A: UMC’s 300mm Fab in Production
Located in Tainan’s Science-based Industrial Park
 Budget: $3.0B, first wafer-out in Q2, 2001
 Currently producing customer products in volume

Gross Die Increases more than Area Ratio
Die size: 12x12 mm2
GDPW
180
GDPW
432
Die size: 20x20 mm2
200 mm
wafer
GDPW
57
300 mm
wafer
GDPW
148
Gross Die Increases More Than Area Ratio
An example:
Die size:22*22 mm
die size
200 m m
300 m m
(m m 2)
G DPW
G DPW
5x5
1108
2602
2.35
7x7
553
1313
2.37
12x12
180
432
2.40
14x14
124
308
2.48
20x20
57
148
2.59
22x22
45
121
2.69
2.8
Ratio
GDPW Ratio
2.6
2.4
2.2
Die size:12*12 mm
2
0
100
200
300
400
Die size (mm sq.)
500
300mm Fab Implications



Larger-Sized Die Will Benefit.
Competitive Or Even Better Yield / D.D.
Shorter Cycle Time For Prototypes Due To
Single Wafer Processing Capability.

Eventual Cost Advantage.

A Game For Major Leaguers: Only Leaders In
IDM, Foundry, DRAM Can Afford Building Fabs.
Technology Advancement Challenges
300mm
Copper
low-k
IPs
90-nm
65-nm
45-nm
IPs
Advanced
lithography
High K
SOI, Strained Si,
novel devices,
IPs
R&D cost and
human resources
ITRS Lithography Roadmap
DRAM half pitch
ASIC/MPU half pitch
ASIC physical gate length
MPU physical gate length
CD (nm) .
250
200
248
150
193
100
157
50
0
1999
2001
2003
2005
Year
2007
EPL & EUV
2009
Lithography Challenges

Mask



Resist material



Lens performance, tool maturity and timing
Alignment accuracy and overlay control
Metrology


Resist maturity and resist processing applications
Exposure tool


Mask performance control and pellicle issue to 157nm
Defect control
Measurement accuracy and precision control
Data engineering and data preparation

OPC implementation and RET techniques
UMC 35nm Gate Patterning

Dense Line
35nm gate is patterned by
aggressive 193nm resist trim.
TEOS
35nm
Iso Line
NMOS Poly in Iso line
CMOS Device Structure Challenges
90nm
65nm
45nm
Bulk Transistor
Bulk Transistor
Bulk Transistor
PD SOI
PD SOI
FD SOI
FD SOI
Strained Si
Double Gate
UMC SOI Device Structure
79 nm
SOI
BOX
UMC Strained-Silicon Device Structure
Poly Gate
Strained-Si
Channel
Co Silicide
Relaxed Si 1-x Ge x
Material from
AmberWave
Systems
UMC Strained Silicon NMOS Gm / Idsat Gain
Strained-Si
800
41%
200
100
100%
NMOS
Vd= 50mV
Idsat (uA/um)
Transconductance, Gm (uS/um)
NMOS
Vg=1.2 V
Strained-Si
80%
70%
Bulk
600
60%
50%
400
40%
Bulk
30%
200
20%
Idlin > 35%
Idsat:23%
0
0
0
0.2
0.4
0.6
Vg (V)
0.8
90%
1
1.2
10%
0%
00
0.2 0.280.4
(W=0.3um, Poly CD ~70 nm)
0.6
0.5675
0.80.8551.0 1.1425
1.2
Vd (V)
• Short Channel NMOS Gm_max increases 41% @ Vd=50 mV.
• Idlin gain ( >30%) is greater than Idsat gain (23%) leading to better
driving capability in circuit operation.
Substrate Material from AmberWave Systems
Id enhancement
1000
300
UMC Interconnect Technology Roadmap
Tecnology Node
0.13um
90nm
65nm
k value
2.7
2.7
2.2
Dielectric Tool
CVD
CVD
Porous CVD / SOD
Al / Cu
Cu
Cu
Cu
Cu Liner
PVD/CVD
PVD/CVD
CVD/ALD
Cu Seed
PVD
PVD/CVD
PVD/ PVD + repair
Cu Fill
Plating
Plating
Plating
UMC 0.13um Cu/Low-K Interconnect Technology
UMC Aggressive R&D Spending


1997-2001 total R&D spending = $ 743 million
Average R&D / Sales % = 8.6%
R&D $million
R&D / Sales %
300
15%
250
R&D Spending
R&D / Sales %
13.3%
10.4%
245
200
150
8.9%
170
12%
9%
153
6.3%
111
6%
100
5.7%
64
3%
50
0
0%
1997
1998
1999
2000
2001
UMC Process Patent Leadership
Number of US Patents
Granted per year
633
700
560
600
500
334
400
300
200
153
172
155
197
100
0
1995
1996
1997
1998
1999
2000
2001
UMC Ranks in the Top 10 for U.S.
Semiconductor Process Technology Patents
Summary I : Technology Challenges

300 mm Wafer: Fab Cost / Technology Challenge.

Lithography Challenge: 90nm to 65nm to 45 nm.

Interconnect Challenge: Low K Dielectric Material.

Ultra Thin Gate: High K Gate Material.

Device Structure: SOI, Strain Silicon Device,
Multi-Gate Device.
Summary II : Global Trends
Fewer semiconductor companies
1
can afford building 300mm fabs and
developing nano-meter technologies
alone.
2
Now
Past
100%
captive
80%
captive
+
20%
outsourcing
Future
50%
captive
+
50%
outsourcing
Outsourcing is the general trend and is doing more for advanced technologies.
3
Business models may be modified to have
more inter-company JDP and JV partnership.