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High Density
ispLSI Families
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 1
Lattice Confidential
High Density
Product Line Expansion
Pins
400+
1998
ispLSI 2000E/2000VE
5000V/8000/ispGDX
300+
1996
ispLSI 1000E/2000V/3000E/6000
240
1994
ispLSI 2000/3000
120
28
0
1992
ispLSI 1000
1985
GAL
0.7K
8K
14K
25K
Logic Density
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 2
Lattice Confidential
50K
ispLSI Families
ispLSI
ispLSI
1000/E
1000/E
ispLSI
2000/E &
2000V/VE
ispLSI
ispLSI
3000
3000
ispLSI
6000
ispLSI
5000V
ispLSI
8000/V
ispLSI 1000/E
ispLSI 2000/E/V/VE ispLSI 3000
ispLSI 6000
ispLSI 5000V
The Premier HighDensity Family
- 125MHz/7.5ns
Pin-to Pin
- 2000 - 8000 PLD
Gates
- 44-Pin to 128Pin Pkgs
SuperFAST System
Performance
- 200MHz/3.5ns
Pin-to-Pin
- 5V/3.3V
- 1000 - 6000 PLD
Gates
- Boundary Scan
Test (VE)
- 44-Pin to 176-Pin
Pkgs
High-Density With
On-Chip Memory
- 70MHz/15ns
Pin-to Pin
- 25,000 PLD
Gates
- 4K Bit FIFO
or RAM
Register/Counte
r
Module
- Boundary
Scan Test
- 208-Pin Pkg
SuperWIDE CPLDs SuperBIG CPLDs
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High Density
January 2008 3
High-Density With
Performance
- 125MHz/7.5ns
Pin-to Pin
- 7000 - 20,000
PLD Gates
- Boundary Scan
Test
- 160-Pin to 432Ball Pkgs
Lattice Confidential
- 125MHz/7.5ns
Pin-to Pin
- 3.3V/2.5V
- 12,000 - 24,000
PLD Gates
- Boundary
Scan Test
- 272-Ball to 388Ball Pkgs
ispLSI 8000/V
- 100MHz/8.5ns
Pin-to Pin
- 5V/3.3V/2.5V
- 25,000 - 50,000
PLD Gates
- Boundary
Scan Test
- 204-Ball to 432Ball Pkgs
Original ispLSI Families (1K/E, 2K and 3K)
Key GAL Features
16V8
22V10 20XV10
Prog. Variable XOR
Macrocell Product
Term
Distribution
20RA10
6002
Asynch Prod. Term
Clocks Sharing/
Input
Registers
ispLSI
GLB
18XVRA4
NOTE: The 3000 Family Utilizes a 24XVRA8 “Twin GLB” Structure
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High Density
January 2008 4
Lattice Confidential
1032 Block Diagram Example
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 5
Lattice Confidential
The 1000/E Family Generic Logic Block
Predictable Propagation Delay
Can Implement 90% of ALL 4-bit MSI Functions
Extremely Flexible and Versatile
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January 2008 6
Lattice Confidential
1000/E Generic Logic Block: Multi Mode
Individual Outputs are Independently Configurable
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High Density
January 2008 7
Lattice Confidential
1000/E Output Routing Pool
–
–
–
–
Connects GLB Outputs to I/O Cells
Greater Flexibility in Pin Assignment
Improved Routibility
Predictable Delay
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High Density
January 2008 8
Lattice Confidential
1000/E Output Routing Pool Bypass
High-Speed Path
Faster Tpd & Tco
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 9
Lattice Confidential
1000/E Family Clock Network
Three Global Clocks
To GLBs
Two Global Clocks
To I/O Cells
ispLSI 1016 has 3 Global Clocks
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High Density
January 2008 10
Lattice Confidential
1000/E Simplified I/O Cell Diagram
© LATTICE SEMICONDUCTOR CORPORATION 2000
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January 2008 11
Lattice Confidential
1000/E I/O Cell Configurations
– Input, Output and Bi-directional Cells
© LATTICE SEMICONDUCTOR CORPORATION 2000
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January 2008 12
Lattice Confidential
ispLSI 1000 Family
Density
(PLD Gates)
2000
4000
6000
8000
Speed:
Fmax (MHz)
111
91
91
80
Speed:
Tpd (ns)
10
12
12
15
Macrocells
64
96
128
192
Registers
96
144
192
288
Inputs & I/Os
36
54
72
106/110
Pins/Package
44-PLCC
44-TQFP
44-JLCC
68-PLCC
100-TQFP
68-JLCC
84-PLCC
100-TQFP
84-CPGA
120-PQFP
128-PQFP
133-CPGA
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 13
Lattice Confidential
ispLSI 1000E Family
Enhancements
• 2nd Generation ispLSI 1000 Product Family
• Identical Pin-Out to ispLSI 1000 Family
– Except for Addition of Global Output Enable Pins
• Provides Much Higher System Performance
– ispLSI 1016
– ispLSI 1016E
Tpd=10ns, Fmax=110 MHz
Tpd=7.5ns, Fmax=125 MHz
• Improved I/O Register Speed for Faster Processor
Bus Applications
• Additional Global OE Pins for Better Tri-State Control
and Higher Performance
• Enhanced GRP Architecture
– More Predictable Delay
– Higher Routability
– Better Utilization
Provides Improvement
Over ispLSI 1000 Family!
• Add Programmable Output Slew Rate Control to
Reduce Ground Bounce and Switch Noise
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 14
Lattice Confidential
ispLSI 1000E Family
Density
(PLD Gates)
2000
6000
8000
Speed:
Fmax (MHz)
125
90/125
91
Speed:
Tpd (ns)
7.5
10/7.5
10
Macrocells
64
128
192
Registers
96
192
288
Inputs & I/Os
36
72
110
Pins/Package
44-PLCC
44-TQFP
84-PLCC
100-TQFP
128-PQFP
128-TQFP
NOW
NOW
NOW
Availability
•
Lattice’s 2nd Generation
1000 Family
•
High System Performance
•
Higher Routability
•
Higher Utilization
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 15
Lattice Confidential
1032 vs. 1032E Comparison
• 1032 and 1032E Identical Except for:
– 1032E Adds 2 Global Output Enables
– 1032E Has Enhanced Routing Resources
• Provides a Performance Migration Path for the 1032
Pinout Difference
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 16
Lattice Confidential
ispLSI 2000 Family
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 17
Lattice Confidential
ispLSI 2000 Family
Product Strategy
• Supports Most Popular Density and I/O Range
– 32 to 128 Macrocells
– 32 to 128 I/O
– 44 to 176 Pin Packages
• Alternative Solution In Terms of Density and I/O Ratio
• Twice As Much I/O for a Given Density as Compared to
ispLSI 1000/E Family
• ispLSI 2000 Family Targeted for
– Highest Performance
– Lowest Cost
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 18
Lattice Confidential
ispLSI 2000 Family Architecture
ispLSI 2064 Block Diagram
Global Output Enables
Megablock Output
Enables
GLB With Optimum
Input-to-Output Ratio
Consistent and
Predictable GRP
Fast or Slow
Slew Rate
Flexible Clocking
Schemes
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 19
Lattice Confidential
ispLSI 2000 Family GLB
JK-,T- and D-type flip flops
20 product terms for all four outputs
Multiple clocks for synchronous
and asynchronous applications
18XVRA4
Product Term Sharing XOR for
combinatorial and registered
functions
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 20
Lattice Confidential
ispLSI 2000 Family ORP
•
1:1 ratio of GLB outputs to I/O Cells
•
Increased routability over the 1000 Family
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 21
Lattice Confidential
ispLSI 2000 Family I/O Cell
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 22
Lattice Confidential
ispLSI 2000 Family Summary
Architecture Enhancements
• Enhanced GRP Architecture
– More Predictable GRP Delay
– Higher Routability
– Better Utilization
• Additional Global OEs
– Enhanced Tri-State Control
– Provide Higher OE Performance
• Eliminates Clock Polarity Option
– Faster Tco
• Provides Output Slew Rate Control
– Reduce Ground Bounce
and Switching Noise
• Emphasizes TQFP Packaging
for ISP Capability
• Eliminates I/O Register
– Faster Tpd
Architecture Optimized for Performance and Cost
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 23
Lattice Confidential
ispLSI 2000 Family
Density
(PLD Gates)
1000
2000
4000
6000
Speed:
Fmax (MHz)
180
125
125
100
Speed:
Tpd (ns)
5.0
7.5
7.5
10
Macrocells
32
64
96
128
Registers
32
64
96
128
Inputs & I/Os
35
70
104
138
Pins/Package
44-PLCC
44-TQFP
48-TQFP
84-PLCC
100-TQFP
128-PQFP
128-TQFP
160-MQFP
176-TQFP
•
Double The I/Os Of 1000
Family
•
Fastest High-Density PLD
Family
•
New TQFP Options Enhance
ISP Capability
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 24
Lattice Confidential
ispLSI 2000 Family
Density vs I/O
2128
128
2096
96
I/Os
1048C/E
2064
64
1032/E
1024
2032
32
1016/E
0
0
32
64
96
128 160 192 224 256
Macrocells
2000 Family Provides Twice the I/O
Compared to 1000/E Family
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 25
Lattice Confidential
ispLSI 2000E Family
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 26
Lattice Confidential
ispLSI 2000V Family
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 27
Lattice Confidential
ispLSI 2000V Family
Product Strategy
• Lattice First 3.3V High-Density Family
• 2000V Family Will Support JTAG Programming Scheme
• Targeted to be Fastest 3.3V CPLD in the Market
• Strengthens Lattice ISP Position
Total
ISP
ispLSI 2000V is the First 3.3V ISP CPLD Family in the Market!
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 28
Lattice Confidential
ispLSI 2000V Family
Density
(PLD Gates)
1000
2000
4000
6000
Speed:
Fmax (MHz)
100
100
80
80
Speed:
Tpd (ns)
7.5
7.5
10
10
Macrocells
32
64
96
128
Registers
32
64
96
128
Inputs & I/Os
35
70/37
104
138/74
Pins/Package
44-PLCC
44-TQFP
44-PLCC
44-TQFP
100-TQFP
84-PLCC
128-PQFP
128-TQFP
176-TQFP
160-PQFP
100-TQFP
84-PLCC
© LATTICE SEMICONDUCTOR CORPORATION 2000
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January 2008 29
Lattice Confidential
•
Industry’s First 3.3V
ISP CPLD Family
•
2000V Family Supports
Open-Drain Outputs
•
Density Migration Path
•
Support Mixed 3.3V/5V
Systems
•
JTAG Programming
ispLSI 3000 Family
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 30
Lattice Confidential
ispLSI 3000 Family
Product Strategy
• High Density / High Functionality / High Speed
• Provides Higher Density and Higher Pin-Count Devices
– 160 to 448 Macrocells
– 130 to 258 I/O Counts
– 160 to 304 Packages
• Increased Functionality for Higher System Integration
• Achieve Highest Performance
– 3192: 10ns (Tpd), 100MHz (Fmax)
• Predictable Delay
• Boundary Scan Testability Supported
Emphasizes Lattice ISP Technology!
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 31
Lattice Confidential
ispLSI 3000 Family Architecture
128 I/Os, 256 Macrocells
384 Registers
Global External and
Internal Clocks
GRP and ORP for Maximum
Routing and Utilization
In-System Programmable
3256 Functional Block Diagram
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 32
Lattice Confidential
ispLSI 3000 Family
Architecture Enhancements
•
Highest Density Device
•
Boundary Scan Testability
•
Twin GLB Architecture
•
More Global Clocks
•
Enhanced GRP Routing
Resources
•
No Fanout Variation In The GRP
•
Global Output Enables
•
Programmable Slew Rate
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 33
Lattice Confidential
ispLSI 3000 Family ORP
• 2:1 ratio of GLB outputs to I/O Cells
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 34
Lattice Confidential
ispLSI 3000 Family I/O Cell
I/O Cell Functionality the Same as the 1000 Family
Test OE to All I/O Cells
Global OEs to All I/O Cells
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 35
Lattice Confidential
ispLSI 3000 Family
Density
(PLD Gates)
7000
9000
11000
12000
14000
20000
Speed:
Fmax (MHz)
125
100
90
100
100
90
Speed:
Tpd (ns)
7.5
10
12
10
10
12
Macrocells
160
192
256
256
320
448
Registers
320
384
384
512
480
672
Inputs & I/Os
162
194
130
258
162
226
Boundary Scan Test
Yes
Yes
Yes
Yes
Yes
Yes
208-MQFP
272-BGA*
NOW
240-MQFP
272-BGA
NOW
160-MQFP
160-PQFP*
NOW
304-MQFP
320-BGA
NOW
208-MQFP
208-PQFP
320-BGA*
NOW
432-BGA
Pins/Package
Availability
* Contact Factory for Availability
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 36
Lattice Confidential
2Q98
Introduction to Vantis
Programmable Logic Devices
MACH 1 and MACH 2 CPLD Families
MACH 5 Family
MACH 4 Family
JTAG ISP
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 46
Lattice Confidential
Agenda
• Vantis value propositions
• Vantis MACH 1 CPLD Family
• Vantis MACH 2 CPLD Family
• Vantis MACH 5 CPLD Family architecture
• Vantis MACH 4 CPLD Family architecture
• Compare and Contrast
• JTAG ISP
© LATTICE SEMICONDUCTOR CORPORATION 2000
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January 2008 47
Lattice Confidential
Vantis Value Propositions
• SpeedLocked performance
• Ease-of-Use
• Multiple Density - I/O combinations
• Reliability
• Advanced system integration features
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 48
Lattice Confidential
Mach 1 and 2
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 49
Lattice Confidential
MACH 1 & MACH 2 Architectures
Principal performance features of the MACH 1 & MACH 2
Architectures are:
• Central switch matrix
• Product-Term (PT) arrays -- programmable “AND” planes
• Logic Allocators -- fixed “OR” planes
• Multimode macrocells
• PAL Block OE (Output Enable) Product-Terms
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 50
Lattice Confidential
MACH 1 & MACH 2 Features and Characteristics
• Original MACH Architectures
• Highly Routable
• Power Management Feature
– Per Macrocell and Per Block power-down
• Guaranteed SpeedLocked Timing
– up to 12 PT for M1
– up to 16 PT for M2
• Multiple Density and I/O Combinations
• Commercial and Industrial Devices Available
• Up to sixteen Product-Term functions are accommodated
© LATTICE SEMICONDUCTOR CORPORATION 2000
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January 2008 51
Lattice Confidential
MACH 1 & MACH 2
Performance: Speeds and Densities
• Speed Performance
– Commercial as fast as tPD = 5 ns (FCNT = 182 MHz)
– Industrial as fast as tPD = 7.5 ns
• Mid-Range Densities
– 32 to 128 macrocells
– 32 to 64 I/Os
– 4 to 16 output enable controls
© LATTICE SEMICONDUCTOR CORPORATION 2000
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January 2008 52
Lattice Confidential
MACH 1 & MACH 2
Performance: System Capabilities
• Devices are In-System Programmable (‘SP’ devices only)
• Devices are JTAG (IEEE 1149.1) compatible (‘SP’ devices only)
– Do not have a boundary-scan register so test is not possible
• PCI-compliant (Speed Grades 7 ns, 10 ns and 12 ns
• Device I/Os are “Bus-Friendly”
• Devices have a programmable security bit
• Devices follow a pre-set power-up procedure
• Power Management Feature -- Full or Half-Power
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 53
Lattice Confidential
MACH 1 & MACH2
Performance: Technology &
Support
• Leading-edge process technology
– The EE6.5 process
– L(EFF) = 0.5 micron
• Supported by DesignDirect and IDE software
• Low-cost entry-level tool
• Windows GUI interface
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 54
Lattice Confidential
MACH 1 & MACH 2 CPLD Families
208
Pins
144
100
MACH131SP-5
MACH131-7
84
MACH231-6
MACH120-12
68
44
MACH231SP-10
MACH221-7
MACH111(SP)-5(5)
MACH215-12
32
Macrocells
MACH211(SP)-7(7)
MACHLV210A-10
48
64
96
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 55
Lattice Confidential
128
256
MACH 1 Block Diagram
PAL Block
Logic
Clock/Input
Pins
P-T
S
w
i
t
c
h
Dedicated
Inputs
M
a
t
r
i
x
26
A
r
r
a
y
(Prog.
AND
Plane)
A
l
l
o
c
a
t
o
r
16
16 Output 16
MCs
(Fixed
OR
Plane)
Output Macrocell Feedback
I/O Pin Feedback
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 56
Lattice Confidential
I/O
Cells
I/O Pins
16
MACH 1 P-T Array & Logic Allocator
Product-Term
Array
To Macrocell
4
From
Switch
Matrix
4
(Max. 12 P-Ts)
4
Programmable
AND- Plane
Fixed OR- Plane
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 57
Lattice Confidential
MACH 1 Macrocell
PAL-Block
Asynchronous
Preset
From Logic (4-12 P-Ts)
Allocator
CLK0
CLKn
1
AP
Q
D
0
AR
PAL-Block
Asynchronous
Preset
To Switch Matrix
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 58
Lattice Confidential
1
0
To I/O Cell
MACH 2 Block Diagram
PAL Block
Logic
P-T
Clock/Input
Pins
S
w
i
t
c
h
22/26
M
a
t
r
i
x
A
l
l
o
c
a
t
o
r
A
r
r
a
y
(Prog.
AND
Plane)
(Fixed
OR
Plane)
8
Output
MCs
8
Buried
MCs
Buried Macrocell Feedback
Output Macrocell Feedback
I/O Pin Feedback
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 59
Lattice Confidential
I/O Pins
I/O
Cells
MACH 2 P-T Array & Logic Allocator
Product-Term
Array
To Macrocell
From
Switch
Matrix
4
(Max. 16 P-Ts)
4
Programmable
AND-Plane
Fixed OR-Plane
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 60
Lattice Confidential
MACH 2 Output Macrocell
PAL-Block
Asynchronous
Preset
1
1
AP
4~16 P-Ts
From Logic Allocator
Block CLK0..CLKn
0
D/T/L Q
AR
PAL-Block
Asynchronous
Reset
To Switch Matrix
© LATTICE SEMICONDUCTOR CORPORATION 2000
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January 2008 61
Lattice Confidential
0
To I/O
Cell
MACH 2 Buried Macrocell
From I/O
Cell
PAL-Block
Asynchronous
Preset
1
4~16 P-Ts
From Logic Allocator
Block CLK0..CLKn
1
0
AP
D/T/L Q
AR
PAL-Block
Asynchronous
Reset
To Switch Matrix
© LATTICE SEMICONDUCTOR CORPORATION 2000
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January 2008 62
Lattice Confidential
0
MACH 1 & MACH 2 Comparison
MACH 1
MACH 2
I/ O
Den sity
Max P-T/ MCell
12
16
PT Clocks
No
MACH 215
Macrocells
1 per I/ O
2 per I/ O
Register
Register
Latch ed
Direct
Registered
Latch ed
26/ 32
Focus
Storage
Elements
Inputs
Inputs per
PAL Block
Direct
26
© LATTICE SEMICONDUCTOR CORPORATION 2000
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January 2008 63
Lattice Confidential
MACH 1 & MACH 2 Summary
• Fastest
• PFQP, TQFP and PLCC packages
• Pin-for pin compatibility
– Between MACH1xx and MACH2xx devices
– MACH111 and MACH 211; MACH131 and MACH231, etc.
• In-System Programmable (ISP) (‘SP’ devices only)
• Commercial and Industrial versions available
• Guaranteed propagation delays -- SpeedLocking
• Universal Software Support
• Full availability
• Cost effective logic solution
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 64
Lattice Confidential
Mach 5
© LATTICE SEMICONDUCTOR CORPORATION 2000
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High Density
January 2008 65
Lattice Confidential
MACH 5(A) CPLD Family Overview
• MACH 5(A) Family Performance Characteristics
• MACH 5(A) Architecture
– MACH 5(A) Internal “Components” and Subsystems
• MACH 5(A) Timing and Delay
© LATTICE SEMICONDUCTOR CORPORATION 2000
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January 2008 66
Lattice Confidential
MACH 5(A) Performance Characteristics
•
Fifth Generation MACH Architecture
•
Hierarchical signal routability
•
Both 5 V and 3.3 V versions
•
Up to 32 Product-Terms per macrocell, with true XOR capability
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January 2008 67
Lattice Confidential
MACH 5(A) Performance Characteristics (cont’d)
• Power Management Feature
– Four PAL block-based power versus speed options
• Synchronous and Asynchronous clocking
–
Single- & Dual-edge clocking
• Fixed, predictable delays
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Performance: Speed and Densities
• High Densities
– 128 to 512 macrocells
– 16 to 64 output enable controls
• Speed Performance
– Commercial tPD = 5.5 ns (fCNT = 182 MHz)
– Industrial tPD = 7.5 ns
• Nine packages offered
– Accommodate from 68 to 256 signal I/Os
• Multiple package/density options
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Performance: System Capabilities
• 5V and 3.3V JEDEC-compliant
• In-System programmable
• JTAG (IEEE 1149.1) compliant
• PCI-compliant (Speed Grades -5, -7, -10 and -12)
•
M5A devices can be hot-socketed
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Performance: System Capabilities (cont’d)
• Mixed supply voltage system-safe
• I/Os are “Bus-Friendly”
–
M5A I/Os have programmable pull-up option
• Individual device I/Os are slew-rate controllable
• Devices have a programmable security bit
• Power Management capability
–
–
Block-by-block basis
Four levels of power reduction
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Lattice Confidential
Performance: Technology and Support
• Leading-edge process technologies:
– EE8 process -- 0.25 micron (Leff), 3.3V
» All M5A devices
– EE7 process -- 0.35 micron (Leff), 3.3V
» M5-320, M5-384, M5-512
» All M5LV (3.3v) devices
– The EE6.5 process -- 0.5 micron (Leff)
» M5-128, M5-192 and M5-256
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Performance: Technology and Support
• Supported by DesignDirect software
– Low-cost entry-level tool with DesignDirect
» Windows GUI interface
» OEM Package with synthesis and simulation
• Supported by Vantis MACHXL software
– Design entry ports to universal tools
• Supported by ispDesignExpert software
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Performance: MACH 5(A) Advancements
• Greater density range
• More I/O and Density points
• More packages
• Higher speed
• More clocking options
• Lower power dissipation
• Lower cost
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Lattice Confidential
MACH 5(A) Architecture
• MACH 5(A) Principal Performance Features:
• Three levels of interconnect
• Product-Term arrays
• Logic Allocators
• Multimode Macrocells
• Control (Clock, Set and Reset) Generators
• OE (Output Enable) Generators
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Lattice Confidential
MACH 5(A) Architecture
Block Level Interconnect
One Large Switch Matrix
Segment Level Interconnect
Non-Hierarchical
One Large switch matrix
(pre-MACH5)
Hierarchical
Distributed switch matrices
(MACH 5(A))
• MACH 5(A) has three levels of interconnect
– Within a PAL block (Local level)
– Within a Group of Four PAL blocks (Block Level)
– Between Segments (Segment Level)
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Lattice Confidential
MACH 5(A) Architecture: Blocks & Segments
Block:
Block
Device
(16 MCs)
Interconnect
I/Os
Segment:
(4 Blocks,
64 MCs)
JTAG
Port
4
Segment Interconnect
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Lattice Confidential
Pin (Global)
4
Clocks
MACH 5(A) Architecture: Device Composition
Segments
2
3
4
5
6
8
PAL Blocks Macrocells
8
128
12
192
16
256
20
320
24
384
32
512
Device*
M5(A)-128/n
M5(A)-192/n
M5(A)-256/n
M5(A)-320/n
M5(A)-384/n
M5(A)-512/n
*n denotes the number of package signal I/Os
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Lattice Confidential
MACH 5(A) Architecture: PAL Block Components
MACH 5(A) PAL Blocks are self-sufficient with their own:
• Product-Term (Logic) Array
• Logic Allocator
• Sixteen Macrocells
• Control Generator
– Clock generator (Four clocks)
– Set/Reset Generator (Three set/reset lines)
• Output Enable (OE) Generator (Two per Block)
• I/O Pin Connections -- function of the higher level
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MACH 5(A) Architecture: PAL Block Layout
OE Generator
2
*Control Generator provides:
4 configurable clocks and
3 configurable set/reset lines.
Block
Interconnect
(16X4 for Macrocells
+4 for clock/clock enable
+3 for set/reset
+2 for output enable)
32
Input register paths
Interconnect
Feeder
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Lattice Confidential
32
2
16
I/Os
Product-Term
array
Macrocells
32
Block
Feeder
Logic Allocator
Control Generator *
MACH 5(A) Architecture: Product-Term Array
A “Cluster” is a sum-of-products function
with either 3 or 4 product terms
Logic
Allocator
Maximum of
5 - 8 Clusters
per Macrocell*
*Maximum allowed depends on Macrocell number.
Each cluster can be directed to only one Macrocell.
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Lattice Confidential
To Macrocell
Block Clock (0-3)
Block Set/Reset (0-2)
MACH 5(A) Architecture: The Macrocell
“Fast”
Path
Combinatorial or
Registered Output
From Logic Allocator
D
Q
Mode
Selection
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Lattice Confidential
O/P
Bfr
&
MUX
To I/O Pin
MACH 5(A) Architecture: Macrocell Modes
• Combinatorial
• D-Type flip-flop
• Latch
• T-Type flip-flop (synthesized)
• J-K flip-flop (synthesized)
• S-R flip-flop (synthesized)
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•
Macrocells 0 and 15 of
each MACH 5(A) PAL
block can be used as
input registers
•
The respective
macrocells must be
accessed via PAL block
I/O pads 3 and 12
•
The output ports of the
input registers can be
directed either to the
matrix as a logic input
to the device or to the
I/O pads of the PAL
block
Block Clock (0-3)
Block Set/Reset (0-2)
MACH 5(A) Architecture: Input Registers
From PAL Block
I/O Pad 3 (MC 0)
or
I/O Pad 12 (MC 15)
D
Q
MC0
or
MC15
Mode
Selection
To Array Logic
(Optional)
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O/P
Bfr
&
MUX
To PAL Block
I/O Pad 0 (MC 0)
or
I/O Pad 15 (MC15)
(Optional)
MACH 5(A) Architecture: Control Generator
• The Control Generator
Consists of the:
– Clock Generator
– Set/Reset Generator
Clock Generator
•
Inputs:
–
–
–
•
Set/Reset Generator
•
Four Synchronous Global Pin Clocks
Four Product-Terms
Three of the Four can be chosen
–
•
Three Product-Terms
Outputs:
–
Outputs:
–
Inputs:
Three Conditioned Block Set/Reset lines
Four Conditioned Block Clock lines
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MACH 5(A) Architecture: Clock Generator
Product-Terms
PT(0:3)
PINCLK
(0:3)
PINCLK0
1 4TO1
2 MUX
3
PINCLK0
1 4TO1
2
MUX
3
CLKIN
PT0
2TO1
MUX
CLK
PT1
PT2
PINCLK0
1 4TO1
2
MUX
3
CE
High Density
January 2008 86
CLK1
CE + EDGE
- EDGE
CE
CLKIN
CLK2
CE
PT3
2TO1
MUX
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2TO1 CLK0
MUX
Lattice Confidential
CLK3
Block
Clock
Lines 0-3
MACH 5(A) Architecture: Set/Reset Generator
Product-Terms
PT(0:2)
SET/RST0
PT0
PT1
2TO1
MUX
SET/RST1
PT2
2TO1
MUX
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SET/RST2
Block
Set/Reset
Lines 0-2
MACH 5(A) Architecture: OE Generator
Output Enable
Generator
Vcc
From
Macrocell
• The Output Buffer can be:
–
–
–
Permanently enabled -- Vcc connected
Permanently disabled -- Ground connected
Selectively enabled -- driven by OE Generator
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One MUX
per I/O
To / From
Device Pin
Input (if Output Buffer
is High Impedance)
MACH 5(A) Architecture: Interconnect
OE Generator
2
•
•
32 Inputs per PAL block
Each Input is an 8:1 MUX
– Seven Inputs from
–
Block Interconnect
– One Input from
–
Local Feedback
Block
Interconnect
Product-Term
array
(16X4 for Macrocells
+4 for clock/clock enable
+3 for set/reset
+2 for output enable)
32
Interconnect
Feeder
2
32
Interconnect Feeder
•
3:1 DEMUX for every signal fed to the Block Interconnect
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16
I/Os
32
Macrocells
Block Feeder
Block
Feeder
Logic Allocator
Control Generator
MACH 5(A) Segment Interconnect Lines
• Block interconnect lines connect to the segment interconnect lines
through a 3 to 1 demultiplexor
• The difference between any two MACH 5(A) densities:
– The number of segments
– The number of Segment Interconnect Lines:
» M5(A)-128 has 128 lines
» M5(A)-192 has 128 lines
» M5(A)-256 has 128 lines
» M5(A)-320 has 152 lines
» M5(A)-384 has 164 lines
» M5(A)-512 has 192 lines
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MACH 5(A) Timing Model: Introduction
• The MACH 5(A) Timing Model is used to estimate delay that a signal
incurs as it passes through the device
• Different input types are subject to different delay factors owing to
the different routing and treatments afforded them
• Different input types shown in the timing model are:
–
–
–
–
Regular inputs and inputs fed back from intern macrocell outputs
Pin (“global”) clock inputs
PT clocks and enables for flip-flops and latches
Inputs directly connected to input registers.
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MACH 5(A) Timing Model
(EXTERNAL FEEDBACK)
(INTERNAL FEEDBACK)
IN
INPUT REG/
INPUT LATCH
TSIR(S/A)
Q
THIR(S/A)
TSIL T
CO(S/A)i
THIL T
PDILi
TSRR T
GOAL
TCES
T
SRi
TCEH
CE
SR
TBLK
TSEG
TPL1
TPL2
TPL3
TPT
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CEH
CE
PIN (“GLOBAL”) CLK
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COMB/ DFF/ LATCH/
TFF*/ SR*/ JK*
* SIMULATED
TS(S/A) T
PD i
TH(S/A)
TCO(S/A)i Q
TSAL
THIAL
TPDLi
TSRR
TGOAL
TCES
TSRi
T
Lattice Confidential
SR
TSLW
TBUF
TEA
TER
OUT
MACH 5(A) Timing Model: Parameters
• Questions related to the application of the MACH 5(A) Timing Model
delay parameters might be as follows for a “regular” input:
– Does the path cross into a second PAL block within the same segment?
» If so, add the tBLK delay constant
– Does the path cross into a PAL block of a different segment?
» If so, add the tSEG delay constant
– Does path involve PAL blocks programmed for reduced power?
» If so, apply the appropriate tPLx delay constant(s)
• If none, some or all of the above apply, consider the appropriate
constants and proceed on the path to the “Logic” delay constants
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MACH 5(A) Timing Model: “Adder” Parameters
•
Product-Term Adder
– tPT: Delay of 0.3 ns delay per PT cluster beyond first
•
Power Management Adders (Technology dependent)
– tPL1: EE6.5: 5.0 ns; EE7: 4 ns; EE8: 4 ns
– tPL2: EE6.5: 9.0 ns; EE7: 6 ns; EE8: 6 ns
– tPL3: EE6.5: 17.5 ns; EE7: 9 ns; EE8: 9 ns
•
Interconnect Adders (Device Speed Grade dependent)
–
–
tBLK:
tSEG:
“-5”: 1.5 ns;
“-5”: 4.5 ns;
“-7”: 1.5 ns; Others: 2.0 ns
“-7”: 5.0 ns; Others: 6.0 ns
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MACH 5(A) Timing Model: Internal Delay
tPDi: Internal combinatorial propagation delay
•
When a signal path utilizes product-terms of more than
one PAL Block:
– tPDi must be considered for each such PAL Block
•
When a signal path utilizes product-terms of a given
PAL Block and is fed back to the same PAL Block to
utilize further product-terms:
– tPDi must be considered for each pass through that PAL Block
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MACH 5(A) I/O and Density Options
• A designer has many macrocell and package options
• MACH 5(A) has a number of macrocell (MC) density and I/O
combinations
• Designing with MACH 5(A) allows designer to consider:
»
»
Six different macrocell densities
Eight (M5) and six (M5A) different I/O options
• Designer can select packages having:
» A given number of I/Os with different MC densities
» A given MC density but different numbers of I/Os
» Beware of “Bond-out” issues with device/package migrations!!
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MACH 5A: Package / Density Options
Pkg Pins (Signal)
I/Os
BGA 352
BGA 256
256
192
PQFP 208
160
PQFP 160
TQFP 144
TQFP 100
120
104
74
Hot-socketing
Pull-up/bus-friendly
tPD = 5.5 ns
tPD = 6.5 ns
M5A-512
M5A-320
M5A-384
M5A-512
M5A-256
M5A-320
M5A-384
M5A-512
M5A-320
M5A-384
M5A-512
M5A-128
M5A-192
M5A-256
M5A-128
M5A-192
M5A-256
M5A-128
M5A-192
M5A-256
128
192
256
320
384
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3.3 or 5V operation
Lattice Confidential
512
Package Type
BGA
PQFP
TQFP
Macrocells
Mach 4
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Lattice Confidential
MACH 4(A) CPLD Family Overview
• Training Module covers:
• MACH 4(A) Family performance features and characteristics
• MACH 4(A) Architecture
– MACH 4(A) internal “components” and subsystems
• MACH 4(A) SpeedLockingTM
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Lattice Confidential
MACH 4(A) Performance Characteristics
• Fourth Generation EE CMOS
MACH Architecture
• Multiple switch matrices
– high routability
– pin locking
• 5 V and 3.3 V versions
• Up to 20 Product-terms per macrocell, with true XOR capability
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MACH 4(A) Performance Characteristics
• Dedicated input registers/latches
• Power management feature
– PAL block-based programmable power-down mode
• Flexible clocking
– Four global clocks with selectable edges
– Synchronous or Asynchronous mode for each macrocell
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Performance: Speed and Densities
• MACH 4
• Densities
–
–
–
–
32 to 256 macrocells
32 to 384 registers
1250 to 10,000 PLD Gates
32 to 128 I/Os
• Speed
– commercial 7.5 ns tPD
– 154 MHz fMAX & 111 MHz
fCNT
• MACH 4A
• Densities
–
–
–
–
32 to 512 macrocells
32 to 768 registers
1250 to 20,000 PLD gates
32 to 256 I/Os
• Speed
– commercial 5.0 ns and 6.5 ns
tPD
– 250 MHz fMAX & 182 MHz
fCNT
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Performance: System Capabilities – I/O
• JTAG (IEEE 1149.1) compliant
– In-System programmable
– boundary scan testing
• PCI-compliant (Speed Grades
– -50/-55/-60/-65/-7/-10/-12)
• 5 V and 3.3 V JEDEC-compliant
– Mixed supply voltage system-safe
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Performance: System Capabilities
• Device I/Os & Inputs
– MACH 4 devices: Bus-friendly
– MACH 4A devices: Programmable Bus-friendly or Pull-up
controlled by one global bit
– Individual I/O slew-rate control
• Programmable security bit prevents:
– Fuse map read-back
– Accidental programming
• Hot-socketing
– In MACH 4A devices
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Performance: Technology and Support
• Leading-edge process technology
– EE8 process: 0.25 mm (Leff), 3.3V
– EE7 process: 0.35 mm (Leff), 3.3V
• Supported by ispDesignExpert, DesignDirect-CPLD, Vantis
MACHXL & MACH-Synario
• Programming Support
–
–
–
–
In-System-Programming using VantisPRO
Industry standard programmers
ATE
Embedded programming
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MACH 4(A) Architecture Overview
• Architecture types
– Based on macrocell to I/O ratio
– 1:1 Architecture and 2:1 Architecture
• Multiple switch matrices
– Input, Central and Output
• PAL blocks
–
–
–
–
–
Product-Term arrays
Logic allocators
Multimode macrocells
I/O cells
Control and OE generators
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Lattice Confidential
M4(A) Multiple Switch Matrix Architecture
CSM
ISM
OSM
PAL
33/34/36
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Lattice Confidential
8\16
MACH 4(A) (2:1 Arch.) Block Diagram
Input
Switch
Matrix
16
MCs
16
16
External Feedback
...
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January 2008 108
I/O Pins
Internal Feedback
PAL Block
Uudet mikropiirit
8
8 I/O Cells
Logic Array
33/34/36
Logic Allocator
Dedicated
Inputs
Central Switch Matrix
Clock/Input
Pins
Output Switch Matrix
PAL Block (33/34/36V16)
Clock
Generator
Lattice Confidential
16
I/O Pins
MACH 4(A) PAL Block Inputs
Device
Number of Inputs to PAL Block
M4A(3,5)-32/32
M4(LV)-32/32
33
M4A(3,5)-64/32
M4(LV)-64/32
33
M4A(3,5)-96/48
M4(LV)-96/48
33
M4A(3,5)-128/64
M4(LV)-128/64
33
M4A(3,5)-192/96
M4(LV)-192/96
34
M4A(3,5)-256/128
M4(LV)-256/128
34
M4A3-384
36
M4A3-512
36
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To Central Switch Matrix
MACH 4(A) (2:1 Arch.) Input Switch Matrix
• Total eight 4:3 muxes per PAL block
• Every 2 macrocells share one 4:3 mux
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From Macrocell 1
MUX
From Macrocell 2
MUX
From I/O Direct
MUX
Registered/latched
MACH 4(A) (2:1 Arch.) Product-Term Logic Array
2:1 arch.
Number of Inputs
1:1 arch.
33/34/36
Number of PTs
90
98
For logic use
80
80
For OE use
8
16
For global PAL
initialization
2
2
Notes:
• M4(A)-192/96 & M4(A)-256/128 have 34 inputs per PAL block
• M4A3-384 & M4A3-512 have 36 inputs per PAL block
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33
Lattice Confidential
MACH 4(A) (2:1 Arch.) Synchronous Logic Allocator
To
n-2
To
n-1
From
n-1
n
n
To From
n+1 n+1
From
n+2
Logic Allocator
– PT cluster steered to 1 of 4 macrocells
– Up to 20 PTs per function
– XOR capability
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To macrocell n
Product Term Cluster
MACH 4(A) (2:1 Arch.) Asynchronous Logic Allocator
To
n-2
To
n-1
From
n-1
n
n
To From
n+1 n+1
From
n+2
Logic Allocator
Where are the other two product terms?
– one for the asynchronous, product-term clocking
– one for the asynchronous set and reset
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Lattice Confidential
To macrocell n
Product Term Cluster
MACH 4(A) (2:1 Arch.) Synchronous Macrocell
Power-Up
Reset
PAL-Block
Initialization
Product Terms
Swap
1
AP AR
0
From Logic Allocator
D/T/L Q
Block CLK0
Block CLK1
Block CLK2
Block CLK3
To Input Switch Matrix
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To Output
Switch
Matrix
MACH 4(A) (2:1 Arch.) Asynchronous Macrocell
Power-Up
Reset
Individual
Initialization
Product Term
Swap
1
AP AR
0
From Logic Allocator
D/T/L Q
Block CLK0
Block CLK1
Individual Clock
Product Term
© LATTICE SEMICONDUCTOR CORPORATION 2000
To Input
Switch Matrix
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To Output
Switch
Matrix
MACH 4(A) (2:1 Arch.) Output Switch Matrix
macrocell
macrocell
macrocell
I/O
Cell
macrocell
I/O
Cell
macrocell
I/O
Cell
macrocell
I/O
Cell
macrocell
MUX
Macrocell drives one of 4 I/Os
I/O
Cell
macrocell
macrocell
I/O can choose one of 8 macrocells
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Lattice Confidential
MACH 4(A) (2:1 Arch.) I/O Cell
Individual OE
Product Term
From Output
Switch Matrix
To Input
Switch Matrix
To Input
Switch Matrix
Q
D/L
Block CLK0
Block CLK1
Block CLK2
Block CLK3
Power-Up Reset
Input register: Programmable Zero-Hold-Time Fuse
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Lattice Confidential
MACH 4(A) (2:1 Arch.) Clock Generator
GCLK0
GCLK1
GCLK2
GCLK3
Block CLK0
(GCLK0 or/GCLK1)
Block CLK1
(GCLK1 or/GCLK0)
Block CLK2
(GCLK2 or/GCLK3)
Block CLK3
(GCLK3 or/GCLK2)
– 4 Clock Signals common to all Macrocells within a PAL Block
– Only 2 global clock signals in M4(A)-32/32 & M4(A)-64/32: GCLK0 connects to
GCLK2; GCLK1 connects to GCLK3
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Lattice Confidential
MACH 4(A) (1:1 Arch.) Block Diagram
Input
Switch
Matrix
16
16
Output
MCs
16
External Feedback
...
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January 2008 119
I/O Pins
Internal Feedback
PAL Block
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16
16 I/O Cells
Logic Array
33
Logic Allocator
Dedicated
Inputs
Central Switch Matrix
Clock/Input
Pins
Output Switch Matrix
PAL Block
(33V16)
Clock
Generator
Lattice Confidential
16
I/O Pins
• Total sixteen 2:2 muxes per
PAL block
• Every macrocell has one 2:2
mux
To Central Switch Matrix
MACH 4(A) (1:1 Arch.) Input Switch Matrix
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Lattice Confidential
MUX
From Macrocell
From I/O Direct
MUX
MACH 4(A) (1:1 Arch.) Product-Term Logic Array
2:1 arch.
Number of Inputs
33/34/36
High Density
January 2008 121
33
Number of PTs
90
98
For logic use
80
80
For OE use
8
16
For global PAL
initialization
2
2
© LATTICE SEMICONDUCTOR CORPORATION 2000
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1:1 arch.
Lattice Confidential
MACH 4(A) (1:1 Arch.) Output Switch Matrix
macrocell
I/O
Cell
macrocell
I/O
Cell
macrocell
I/O
Cell
macrocell
I/O
Cell
macrocell
MUX
I/O
Cell
macrocell
I/O
Cell
macrocell
I/O
Cell
macrocell
I/O
Cell
macrocell
Macrocell can drive
one of 8 I/Os
I/O can choose
one of 8 macrocells
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I/O
Cell
MACH 4(A) (1:1 Arch.) I/O Cell
Individual OE
Product Term
From Output
Switch Matrix
To Input
Switch Matrix
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Lattice Confidential
MACH 4(A) Architectures Comparison
1:1 Arch.
2:1 Arch.
MC to I/O Ratio
1:1
2:1
Focus
I/O
Density
Max PT/MC
20
20
PT Clocks
Yes
Yes
Storage Elements Register/Latch
Register/Latch
Input Types
Direct
Direct/Registered/Latched
Inputs/PAL Block
33
33/34/36
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Lattice Confidential
MACH 4(A) SpeedLockingTM
• SpeedLocking assures guaranteed timing
– independent of the path taken through device
• No expander or PT adders required
• Ensures complete predictability
• All MACH 4(A) devices have SpeedLocking
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Lattice Confidential
MACH 4(A) Timing Model
External Feedback
Internal Feedback
IN
COMB / DFF / TFF /
LATCH / SR* / JK*
* simulated
Central
Switch
Matrix
tPL
INPUT REG/
INPUT LATCH
tSIRS
tHIRS
tSIL
tHIL
tSIRZ
tHIRZ
tSILZ
tHILZ
tPDILi
tICOSi
tIGOSi
tPDILZi
Q
tSS(T)
tSA(T)
tH(S/A)
tS(S/A)L
tH(S/A)L
tSRR
tPDi
tPDLi Q
tCO(S/A)i
tGO(S/A)i
tSRi
S/R
PIN CLK
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Lattice Confidential
tSLW
OUT
tBUF
tEA
tER
MACH 4(A) Timing Model
Adder Parameters
Output Buffer
tBUF : Output Buffer delay adder
tSLW: Slow slew rate delay adder
Low Power
tPL : Power down mode delay adder
Notes:
• tPL is an adder to setup time in synchronous data path
• tPL is an adder to clock to output time in asynchronous data path
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Lattice Confidential
MACH 4 Product Selection Guide
Feature
M4(LV)-32/32
M4(LV)-64/32
M4(LV)-96/48
M4(LV)-128/64
M4(LV)-192/96
M4(LV)-256/128
MC
32
64
96
128
192
256
I/O
32
32
48
64
96
128
IN
2
2
8
6
16
14
Ck
2
2
4
4
4
4
OE
32
32
48
64
96
128
FF Icc (mA)
Packages
32 25 44PLCC, 44TQFP, 48TQFP
96 25 44PLCC, 44TQFP, 48TQFP
144 50
100TQFP
192 70
100PQFP, 100TQFP
288 85
144TQFP
384 100
208PQFP, 256BGA
MACH 4 devices are available in:
-7/-10/-12/-15 commercial grade
-10/-12/-14/-18 industrial grade
Devices are dual-marked with commercial and industrial grades
with industrial marks are one-speed grade slower, e.g. M4LV-256/128-7VC -10VI
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Lattice Confidential
MACH 4A Product Selection Guide
Feature
MC I/O IN Ck OE FF
Packages
M4A(3,5)-32/32
32
32
2
2
32
32
44PLCC, 44TQFP, 48TQFP
M4A(3,5)-64/32
64
32
2
2
32
96
44PLCC, 44TQFP, 48TQFP
M4A(3,5)-96/48
96
48
8
4
48 144
100TQFP
M4A(3,5)-128/64 128 64
6
4
64 192
100PQFP, 100TQFP
M4A(3,5)-192/96 192 96 16 4
96 288
144TQFP
M4A(3,5)-256/128 256 128 14 4 128 384
208PQFP, 256BGA
M4A3-384
384 192 0
4 192 576
176TQFP(128), 208PQFP(160), 256BGA(192)
M4A3-512
512 256 0
4 256 768 176TQFP(128), 208PQFP(160), 256BGA(192), 352BGA(256)
MACH 4A devices have following speed options: (contact Vantis rep for availability)
-50/-55/-60/-65/-7/-10/-12 commercial grade, -7/-10/-12/-14 industrial grade
Devices are dual-marked with commercial and industrial grades e.g. M4A3-256/128-7VC -10VI
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Lattice Confidential
MACH 4A Package Migration
M4A-512/256
(3V only)
6.5 ns
352 BGA
Note: All devices in same
package are footprint compatible.
Where a device has less I/Os it is
a subset of other devices
256 BGA
208 PQFP
M4A-256/128
(3V & 5V)
5.0 ns
176 TQFP
100 TQFP/PQFP
(*M4A-96/48 is only in 100TQFP)
M4A-32/32
(3V & 5V)
5.0 ns
M4A-64/32
(3V & 5V)
5.0 ns
32
64
*M4A-96/48
(3V & 5V)
5.0 ns
High Density
January 2008 130
M4A-384/160
(3V only)
6.5 ns
M4A-512/160
(3V only)
6.5 ns
M4A-384/128
(3V only)
6.5 ns
M4A-512/128
(3V only)
6.5 ns
M4A-128/64
(3V & 5V)
5.0 ns
Macrocells
96
128
192
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M4A-512/192
(3V only)
6.5 ns
M4A-192/96
(3V & 5V)
5.0 ns
144 TQFP
44 PLCC
48 TQFP
44 TQFP
M4A-384/192
(3V only)
6.5 ns
Lattice Confidential
256
384
512
ispLSI and Mach Comparison
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Lattice Confidential
Compare and Contrast
• Architecture
• Performance
• System Integration Features
• Two Comparisons
– ispLSI2032VE -vs- M4A3-32/32
– ispLSI5512V -vs- M4A-512/256
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M4A3-32/32 -vs- ispLSI 2032VE
Architecture
Feature
M4A3-32/32
IspLSI 2032VE
Macrocells
I/Os + Inputs
32
2 Blocks
32 + 2
32
8 GLBs
32 + 3
Inputs to Array
33
18/GLB
PT Allocation
Steering
Sharing
Asynchronous
Y
Y
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M4A3-32/32 -vs- ispLSI 2032VE
Performance
Feature
M4A3-32/32
IspLSI 2032VE
tPD
5.0ns
4.0ns/6.0ns
tCO
4.0ns
4.0ns
tSU
3.0ns
3.5ns
Programming
Time
4.2 sec
1 sec
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Lattice Confidential
M4A3-32/32 -vs- ispLSI 2032VE
Features
Feature
M4A3-32/32
IspLSI 2032VE
JTAG ISP
Y
Y
I/O Voltage
3.3, 5.0
3.3, 5.0
IOL
24mA
8mA
Programming
Cycles
100
10,000
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Lattice Confidential
M4A3-512 -vs- ispLSI 5512V
Architecture
Feature
M4A3-512
IspLSI 5512V
Macrocells
I/Os
512
32 Blocks
Up to 256
512
16 GLBs
Up to 288
Inputs to Array
36
68
PT Allocation
Steering
Sharing
Asynchronous
Y
Y
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M4A3-512 -vs- ispLSI 5512V
Performance
Feature
M4A3-512
IspLSI 5512V
tPD
7.5ns
8.5ns/10ns
tCO
5.5ns
5.0ns
tSU
5.5ns
7.5ns
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Lattice Confidential
M4A3-512 -vs- ispLSI 5512V
Features
Feature
M4A3-512
IspLSI 5512V
JTAG ISP
Y
Y
I/O Voltage
3.3, 5.0
2.5, 3.3, 5.0
IOL
24mA
8mA
Programming
Cycles
100
10,000
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Lattice Confidential
Comparison Summary
• ispLSI and MACH architectures have significant differences and
similarities
• Differences:
– Basic architecture and structure of routing schemes
– Macrocell features
These differences make the architectures complimentary.
• Similarities:
– Feature sets
– Performance
The similarities allow the architectures to work together.
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Lattice Confidential
ISP
© LATTICE SEMICONDUCTOR CORPORATION 2000
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Lattice Confidential
MACH JTAG & ISP Overview
• MACH parts having JTAG and In-System Programming (ISP)
capabilities
• JTAG
» Boundary Scan tests
» Software vendors
• In-System Programming (ISP)
»
»
»
»
Benefits of ISP
Concurrent ISP
ISP Procedures and resources
Software tools overview
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Lattice Confidential
JTAG 5-Pin Standard and Vantis 6-Pin Interface
• JTAG 5-Pin Standard programming port adds an optional TRST*
(Test Reset) pin:
– used to asynchronously reset the TAP controller
– active LOW -- connect to Vcc/HIGH when not used
• Vantis 6-Pin Interface adds an ENABLE* pin for some MACH4xx
parts:
– Used for programming
– Active LOW -- connect to GND/LOW if not required
– Devices using the Vantis 6-pin port are M4-96/96, M4-128 and M4-256 only
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Lattice Confidential
MACH Devices with the JTAG Feature
•
MACH JTAG-ISP parts with JTAG
4-pin standard:
–
–
–
–
–
–
–
MACH1XXSP**
MACH2XXSP**
MACH4-32
MACH4-64
MACH4-96/48
MACH4-192
MACH5XX
•
JTAG-ISP parts with Vantis 6-pin
programming port:
– MACH4-96/96
– MACH4-128
– MACH4-256
•
To comply with JTAG 4-pin
standard, connect TRST* to HIGH
and ENABLE* to LOW
** MACH 1 and MACH 2 Devices are
JTAG-Compatible but not JTAG-Compliant
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Lattice Confidential
JTAG Instructions
• Public and Private Instructions
• IEEE 1149.1/JTAG-compliant devices have the following mandatory
public instructions:
– BYPASS
– SAMPLE/PRELOAD
– EXTEST
• MACH 1XXSP and 2XXSP parts have only the BYPASS instruction
– No JTAG test capability, yet JTAG-compatible
• Private Instructions are used only by the manufacturer
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Lattice Confidential
JTAG Optional Public Instructions
• Other public instructions include:
– IDCODE
– HIGH-Z
– USERCODE (MACH 4 devices only)
• MACH devices have private instructions for programming and
testing
– Used by Vantis for internal testing
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Lattice Confidential
MACH In-System Programming
• No special programming pins required for MACH devices
• Regular 4-pin JTAG-standard port used to shift in:
– Programming instructions
– Programming data
• Multiple MACH devices can be programmed in a serial boundary
scan chain
– Non-Vantis devices are put in BYPASS mode
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Vcc-Independent Signal Level Programming
• MACH devices are Vcc level-independent programmable
• Devices powered by 5v and 3.3v can be programmed with the same
data voltage level -- independent of Vcc level
• Programmable MACH devices with Vcc of 5v or 3.3v require data
signals of 5v or less for In-System Programming
• Devices powered by 5v and 3.3v Vcc levels can be included in the
same chain
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Lattice Confidential
MACH JTAG-ISP Software
• VantisPRO (formerly MACHPRO)
• In-System Programming on a PC
– DOS, Win 3.1, Win95 and Win NT 4.x versions
– DOS version is ideal for batch programming
• In-System Programming on Automated Test Equipment (ATE)
– Use the output from VantisPRO for
» HP3070
» Teradyne
» GenRad
» Asset Intertech
• Embedded Programming
– Code is resident in an on-board microprocessor
– Allows for remote design update
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Lattice Confidential
VantisPRO
• Programs MACH devices in a JTAG chain having other non-Vantis
JTAG-compliant devices
• Uses MACH JEDEC maps generated by any MACH design software
tool
• Bulk erases the device
• Serializes the JEDEC (fusemap) file
• Bypasses devices not to be programmed
• Shifts the JEDEC data into the device
• Programs JEDEC data into the appropriate cells
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Lattice Confidential
JTAG-ISP Programming Cable
•
Cable plugs directly into a IBM-compatible PC parallel port
•
Lattice cable can be used by selecting
– Project|Advanced Options…|Use Alternate Port Mapping
Parallel Port
PC
JTAG
Device
Ten-Wire Cable
4-wires:
1-wire:
1-wire:
1-wire:
3-wires:
Standard JTAG
TRST*
ENABLE*
Vcc
Ground
Target Board
MACH4
-96
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MACH5
-128
Lattice Confidential
MACH5
-256
In-System Programming Procedure
• Use DesignDirect software to create a JEDEC (fusemap) file
• Load VantisPRO software onto the PC
– With DesignDirect, VantisPRO is already loaded by default
• Create a Chain file describing the JTAG chain
– List devices in order from TDI to TDO
– Specify “program” or “bypass” for each device
– The Chain file may consist of a single device
• VantisPRO does the rest!
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In-System Programming Resources
WHAT YOU NEED
WHERE TO FIND IT
 JEDEC File
 Any CAE tool that supports
Vantis
 VantisPRO
 www.vantis.com, Vantis Sales
 Cable Schematic
 www.vantis.com, Vantis Sales
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Lattice Confidential
Concurrent Programming of Multiple Devices
•
VantisPRO can program many devices at once
•
Programming “wait” time is shared between all
devices
•
Verification is performed serially
•
Concurrent programming further reduces costs of
programming
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MACH Concurrent Programming on the HP 3070
JTAG Chain Size
Program and Pattern
Verify Time
(HP 3070 @ 1 MHz)
(1) MACH4-128
4.7 seconds
(3) MACH4-128
5.3 seconds
(10) MACH4-128
7.9 seconds
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Concurrent Programming of Multiple Devices
•
10 MACH devices ATE-programmed in less than 8 seconds
•
Some fast PCs can accomplish the same in 50 to 60 seconds
(Non-Vantis
Device)
(Non-Vantis
Device)
BYPASS
BYPASS
TDO
TMS
TCK
(Non-Vantis
Device)
TDI
BYPASS
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MACH Starter Kit
• MACH Starter Kit includes:
–
–
–
–
Software - CD ROM with DesignDirect Base software and VantisPRO
Programming cable - Six-foot long and buffered
MACH ISP demo board with M4-32/32-7JC & M4-64/32-7JC sample devices
MACH ISP manual
• VantisPRO software and cable schematic information available at:
– Web site: www.vantis.com
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Literature and Support
• www.vantis.com/literature has all data sheets and application notes
available. There are always additional in development.
• [email protected] can answer all questions regarding MACH
devices and software.
• Technical call center: (888)VANTIS-1
• Reference design program for IP needs
– SDRAM Controller
– PCI Target
– Page-mode DRAM Controller
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