Transcript pptx - Computer Sciences Dept.

21st Century
Computer Architecture
A community white paper
NSF Outbrief on June 22, 2012
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Information & Commun. Tech’s Impact
Semiconductor Technology’s Challenges
Computer Architecture’s Future
Pre-Competitive Research Justified
Process, Participants & Backups
20th Century ICT Set Up
• Information & Communication Technology (ICT)
Has Changed Our World
o <long list omitted>
• Required innovations in algorithms, applications,
programming languages, … , & system software
• Key (invisible) enablers (cost-)performance gains
o Semiconductor technology (“Moore’s Law”)
o Computer architecture (~80x per Danowitz et al.)
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Enablers: Technology + Architecture
Architecture
Technology
Danowitz et al., CACM 04/2012, Figure 1
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21st Century Promise
• ICT Promises Much More
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Data-centric personalized health care
Computation-driven scientific discovery
Human network analysis
Much more: known & unknown
• Characterized by
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Big Data
Always Online
Secure/Private
…
Whither enablers of future (cost-)performance gains?
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Technology’s Challenges 1/2
Late 20th Century
The New Reality
Moore’s Law —
2× transistors/chip
Transistor count still 2× BUT…
Dennard Scaling —
~constant power/chip
Gone. Can’t repeatedly double
power/chip
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Classic CMOS Dennard Scaling:
the Science behind Moore’s Law
Source: Future of Computing Performance:
Game Over or Next Level?,
National Academy Press, 2011
Scaling:
Voltage:
Oxide:
(Finding 2)
V/a
tOX/a
Results:
1/a2
Power/ckt:
Power Density: ~Constant
National Research Council (NRC) – Computer Science and Telecommunications Board (CSTB.org)
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Post-classic CMOS Dennard Scaling
Post Dennard CMOS Scaling Rule
TODO:
Chips w/ higher power (no), smaller (),
Scaling:
dark silicon (), or other (?)
Voltage:
V/a V
tOX/a
Oxide:
Results:
1/a2 1
Power/ckt:
Power Density: ~Constant a2
National Research Council (NRC) – Computer Science and Telecommunications Board (CSTB.org)
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Technology’s Challenges 2/2
Late 20th Century
The New Reality
Moore’s Law —
2× transistors/chip
Transistor count still 2× BUT…
Dennard Scaling —
~constant power/chip
Gone. Can’t repeatedly double
power/chip
Modest (hidden)
transistor unreliability
Increasing transistor unreliability
can’t be hidden
Focus on computation
over communication
Communication (energy) more
expensive than computation
1-time costs amortized
via mass market
One-time cost much worse &
want specialized platforms
How should architects step up as technology falters?
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21st Century Comp Architecture
20th Century
21st Century
Single-chip in
generic
computer
Architecture as Infrastructure:
Spanning sensors to clouds
X
Performance plus security, privacy, Crossavailability, programmability, …
Cutting:
Performance
via invisible
instr.-level
parallelism
Energy First
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Parallelism
X
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Specialization
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Cross-layer design
Predictable
technologies:
CMOS, DRAM,
& disks
New technologies (non-volatile
memory, near-threshold, 3D,
photonics, …) Rethink: memory &
storage, reliability, communication
Break
current
layers with
new
interfaces
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What Research Exactly?
• Example
o Dream of sensor/phone apps that burn >> 1W package
o Note: Short-term use often followed by long idle period
o Exploit “Computational Sprinting” (to idle!)
• 16 cores (32W) for 100s ms in 1W package
• Use phase-change material thermal “capacitor”
• Research areas in white paper (& backup slides)
1.
2.
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Architecture as Infrastructure: Spanning Sensors to Clouds
Energy First
Technology Impacts on Architecture
Cross-Cutting Issues & Interfaces
• Computation Sprinting funded NSF CCF-1161505
• Much more research developed by future PIs!
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Validating Thermal Models
Source: Computational Sprinting (talk) NSF CCF-1161505
Raghavan, Luo, Chandawalla, Papaefthymiou, Pipe, Wenisch & Martin
HPCA 2012 (http://www.cis.upenn.edu/acg/papers/DaSi-talk.pptx)
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Pre-Competitive Research Justified
• Retain (cost-)performance enabler to ICT revolution
http://cra.org/ccc/docs/init/21stcenturyarchitecturewhitepaper.pdf
• Successful companies cannot do this by themselves
o Lack needed long-term focus
o Don’t want to pay for what benefits all
o Resist transcending interfaces that define their products
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White Paper Process
• Late March 2012
o CCC contacts coordinator & forms group
• April 2012
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Brainstorm (meetings/online doc)
Read related docs (PCAST, NRC Game Over, ACAR1/2, …)
Use online doc for intro & outline then parallel sections
Rotated authors to revise sections
• May 2012
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Brainstorm list of researcher in/out of comp. architecture
Solicit researcher feedback/endorsement
Do distributed revision & redo of intro
Release May 25 to CCC & via email
Kudos to participants on executing on a tight timetable
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White Paper Participants
Sarita Adve, U Illinois *
David H. Albonesi, Cornell U
David Brooks, Harvard U
Luis Ceze, U Washington *
Sandhya Dwarkadas, U Rochester
Joel Emer, Intel/MIT
Babak Falsafi, EPFL
Antonio Gonzalez, Intel/UPC
Mark D. Hill, U Wisconsin *,**
Mary Jane Irwin, Penn State U *
David Kaeli, Northeastern U *
Stephen W. Keckler, NVIDIA/U Texas
Christos Kozyrakis, Stanford U
Alvin Lebeck, Duke U
Milo Martin, U Pennsylvania
José F. Martínez, Cornell U
Margaret Martonosi, Princeton U *
Kunle Olukotun, Stanford U
Mark Oskin, U Washington
Li-Shiuan Peh, M.I.T.
Milos Prvulovic, Georgia Tech
Steven K. Reinhardt, AMD
Michael Schulte, AMD/U Wisconsin
Simha Sethumadhavan, Columbia U
Guri Sohi, U Wisconsin
Daniel Sorin, Duke U
Josep Torrellas, U Illinois *
Thomas F. Wenisch, U Michigan *
David Wood, U Wisconsin *
Katherine Yelick, UC Berkeley/LBNL *
“*” contributed prose; “**” effort coordinator
Thanks of CCC, Erwin Gianchandani & Ed Lazowska for
guidance and Jim Larus & Jeannette Wing for feedback
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Back Up Slides
• Detailed research areas in white paper
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2.
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Architecture as Infrastructure: Spanning Sensors to Clouds
Energy First
Technology Impacts on Architecture
Cross-Cutting Issues & Interfaces
http://cra.org/ccc/docs/init/21stcenturyarchitecturewhitepaper.pdf
• Findings on National Academy “Game Over” Study
• Glimpse at DARPA/ISAT Workshop “Advancing
Computer Systems without Technology Progress”
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1. Architecture as Infrastructure:
Spanning Sensors to Clouds
• Beyond a chip in a generic computer
• To pillar of 21st century societal infrastructure.
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o
o
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Computation in context (sensor, mobile, …, data center)
Systems often large & distributed
Communication issues can dominate computation
Goals beyond performance (battery life, form factor)
• Opportunities (not exhaustive)
o Reliable sensors harvesting (intermittent) energy
o Smart phones to Star Trek’s medical “tricorder”
o Cloud infrastructure suitable for both “Big Data” streams
& low-latency qualify-of-service with stragglers
o Analysis & design tools that scale
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2. Energy First
• Beyond single-core performance computer
• To (cost-)performance per watt/joule
• Energy across the layers
o Circuit/technology (near-threshold CMOS, 3D stacking)
o Architecture (reducing unnecessary data movement)
o Software (communication-reducing algorithms)
• Parallelism to save energy
o Vast (fined-grained) homogeneous & heterogeneous
o Improved SW stack
o Applications focus (beyond graphic processing units)
• Specialization for performance & energy efficiency
o Abstractions for specialization (reducing 1-time cost)
o Energy-efficient memory hierarchies
o Reconfigurable logic structures
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3. Technology Impacts on Architecture
• Beyond CMOS, Dram, & Disks of last 3+ decades to
• Using replacement circuit technologies
o Sub/near-threshold CMOS, QWFETs, TFETs, and QCAs
• Non-volatile storage
o Beyond flash memory to STT-RAM, PCRAM, & memristor
• 3D die stacking & interposers
o logic, cache, small main memory
• Photonic interconnects
o Inter- & even intra-chip
• Design automation
o from circuit-design w/ new technologies to
o pre-RTL functional, performance, power, area modeling of
heterogeneous chips & systems
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4. Cross-Cutting Issues & Interfaces
• Beyond performance w/ stable interfaces to
• New design goals (for pillar of societal infrastructure)
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Verifiability (bugs kill)
Reliability (“dependability” computing base?)
Security/Privacy (w/ non-volatile memory?)
Programmability (time to correct-performant solution)
• Better Interfaces
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High-level information (quality of service, provenance)
Parallelism ((in)dependence, (lack of) side-effects)
Orchestrating communication ((recursive) locality)
Security/Reliability (fine-grain protection)
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Executive summary (Added to National Academy Slides)
 Highlights of National Academy Findings
(F1) Computer hardware has transitioned to multicore
(F2) Dennard scaling of CMOS has broken down
(F3) Parallelism and locality must be exploited by software
(F4) Chip power will soon limit multicore scaling
 Eight recommendations from algorithms to education
 We know all of this at some level, BUT:
Are we all acting on this knowledge or hoping for business as usual?
Thinking beyond next paper to where future value will be created?
– Questions Asked but Not Answered Embedded in NA Talk
– Briefly Close with Kübler-Ross Stages of Grief:
Denial  …  Acceptance
Source: Future of Computing Performance: Game Over or Next Level?,
National Academy Press, 2011
Mark Hill talk (http://www.cs.wisc.edu/~markhill/NRCgameover_wisconsin_2011_05.pptx)
System Capability (log)
The Graph
Fallow Period
80s
90s
00s
10s
20s
30s
40s
50s
Source: Advancing Computer Systems without Technology Progress,
ISAT Outbrief (http://www.cs.wisc.edu/~markhill/papers/isat2012_ACSWTP.pdf)
Mark D. Hill and Christos Kozyrakis, DARPA/ISAT Workshop, March 26-27, 2012.
Approved for Public Release, Distribution Unlimited
The views expressed are those of the author and do not reflect the official policy or position of the
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Department of Defense or the U.S. Government.
Surprise 1 of 2
• Can Harvest in the “Fallow” Period!
• 2 decades of Moore’s Law-like perf./energy gains
• Wring out inefficiencies used to harvest Moore’s Law
HW/SW Specialization/Co-design (3-100x)
Reduce SW Bloat (2-1000x)
Approximate Computing (2-500x)
--------------------------------------------------~1000x = 2 decades of Moore’s Law!
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“Surprise” 2 of 2
• Systems must exploit LOCALITY-AWARE parallelism
• Parallelism Necessary, but not Sufficient
• As communication’s energy costs dominate
• Shouldn’t be a surprise, but many are in denial
• Both surprises hard, requiring “vertical cut” thru SW/HW
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