Transcript Ch. 5 Slides - Computer Science

Chapter 5: Computer Systems
Organization
Invitation to Computer Science,
C++ Version, Third & Fourth Edition
Added to by S. Steinfadt - Spring 2008
Additional source from J. Baker and M.
Scherger’s slides
Objectives
In this chapter, you will learn about:

The components of a computer system

Putting all the pieces together – the Von
Neumann architecture

The future: non-Von Neumann architectures
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Machine Language Instructions
Instruction
0
Load
1
Store
2
Clear
3
Add
4
Increment
5
Subtract
6
Decrement
7
Compare
8
Jump
9
Jump GT
10
Jump EQ
11
Jump LT
12
Jump NEQ
13
In
14
Out
15
Halt
Binary Op Code Meaning
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Introduction

Computer organization examines the computer
as a collection of interacting “functional units”

Functional units may be built out of the circuits
already studied

Higher level of abstraction assists in
understanding by reducing complexity
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Figure 5.1
The Concept of Abstraction
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The Components of a Computer
System

Von Neumann architecture has four functional
units:

Memory

Input/Output

Arithmetic/Logic unit

Control unit

Sequential execution of instructions

Stored program concept
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Figure 5.2
Components of the Von Neumann Architecture
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Computer Organization

Logical organization of computer
Memory
Input
CPU
ALU
Output
Secondary
Storage
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Memory and Cache

Information stored and fetched from memory
subsystem

Random Access Memory maps addresses to
memory locations

Cache memory keeps values currently in use in
faster memory to speed access times
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Memory and Cache (continued)

RAM (Random Access Memory) Often called
memory, primary memory

Memory made of addressable “cells”

Current standard cell size is 8 bits

All memory cells accessed in equal time

Memory address

Unsigned binary number N long

Address space is then 2N cells
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Memory and Cache (continued)



Rapid access, low capacity “warehouse”
Retains information entered through input unit
Retains info that has already been processed until
can be sent to output unit
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Figure 5.3
Structure of Random Access Memory
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Powers of 2 - How much
information?
10





2 = 1K = 1024
1KB = 1 kilobyte
220 = 1M = 1,048,576
1MB = 1 megabyte
230 = 1G = 1,073,741,824 1GB = 1 gigabyte
240 = 1T = 1,099,511,627,776 1TB = 1 terabyte
250 = 1P = 1,125,899,906,842,624 1PB = 1 petabyte
If you have 16 address bits to address bytes…
 216 = 26 * 210 = 64 * 210 = 64KB = 65,536 bytes
 How many bits is that?
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Powers of 10
Quantity in Bytes
Base-10
Value
Amount of Textual
Information
1 byte
100
One character
1 kilobyte
103 ≈ 210
One typed page
1 megabyte
106 ≈ 220
Two or three novels
1 gigabyte
109 ≈ 230
A departmental library or a
large personal library
1 terabyte
1012 ≈ 240
The library of a major
academic research
university
More examples and information at http://www2.sims.berkeley.edu/research/projects/howmuch-info/datapowers.html
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Memory and Cache (continued)

Parts of the memory subsystem

Fetch/store controller

Fetch: retrieve a value from memory

Store: store a value into memory

Memory address register (MAR)

Memory data register (MDR)

Memory cells, with decoder(s) to select individual
cells
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Memory and Cache (continued)

Fetch operation



The address of the desired memory cell is moved
into the MAR
Fetch/store controller signals a “fetch,” accessing
the memory cell
The value at the MAR’s location flows into the
MDR
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Memory and Cache (continued)

Store operation

The address of the cell where the value should go
is placed in the MAR

The new value is placed in the MDR

Fetch/store controller signals a “store,” copying
the MDR’s value into the desired cell
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Memory and Cache (continued)

Memory register

Very fast memory location

Given a name, not an address

Serves some special purpose

Modern computers have dozens or hundreds of
registers
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Figure 5.7
Overall RAM Organization
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Cache Memory

Memory access is much slower than processing
time

Faster memory is too expensive to use for all
memory cells

Locality principle


Once a value is used, it is likely to be used again
Small size, fast memory just for values currently
in use speeds computing time
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Input/Output and Mass Storage

Communication with outside world and external data
storage

Input unit


“Receiving” section of computer
Obtains data from input devices



Usually a keyboard, mouse, disk or scanner
Places data at disposal of other units
2. Output unit


“Shipping” section of computer
Puts processed info on various output devices


Screens, paper printouts, speakers
Makes info available outside the computer
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Input/Output and Mass Storage


Human interfaces: monitor, keyboard, mouse

Archival storage: not dependent on constant
power
External devices vary tremendously from each
other
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Input/Output and Mass Storage
(continued)

Volatile storage



Information disappears when the power is turned
off
Example: RAM
Nonvolatile storage


Information does not disappear when the power is
turned off
Example: mass storage devices such as disks
and tapes
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Input/Output and Mass Storage
(continued)

Mass (secondary) storage devices


Direct access storage device

Hard drive, CD-ROM, DVD, etc.

Uses its own addressing scheme to access data
Sequential access storage device

Tape drive, etc.

Stores data sequentially

Used for backup storage these days
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Input/Output and Mass Storage
(continued)

Mass or Secondary storage unit

Long-term, high-capacity “warehouse”
Stores programs or data not currently being used by
other units on secondary storage devices (like discs)
Takes longer to access than primary memory

data location


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Input/Output and Mass Storage
(continued)

Direct access storage devices

Data stored on a spinning disk

Disk divided into concentric rings (sectors)

Read/write head moves from one ring to another
while disk spins

Access time depends on:

Time to move head to correct sector

Time for sector to spin to data location
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Figure 5.8
Overall Organization of a Typical Disk
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Input/Output and Mass Storage
(continued)

I/O controller

Intermediary between central processor and I/O
devices

Processor sends request and data, then goes on
with its work

I/O controller interrupts processor when request is
complete
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Figure 5.9
Organization of an I/O Controller
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The Arithmetic/Logic Unit

Arithmetic and Logic Unit


“Manufacturing” section of computer
Contains decision mechanisms and can make comparisons

Actual computations are performed

Primitive operation circuits

Arithmetic [+, -, *, /]

Comparison [equality or CE, GT, LT, NEQ]

Logic [AND, OR, NOT, XOR]

Data inputs and results stored in registers

Multiplexor selects desired output
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Figure 5.12
Using a Multiplexor Circuit to Select the Proper ALU Result
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The Arithmetic/Logic Unit
(continued)

ALU process

Values for operations copied into ALU’s input
register locations

All circuits compute results for those inputs

Multiplexor selects the one desired result from all
values

Result value copied to desired result register
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The Control Unit

Manages stored program execution

Task

Fetch from memory the next instruction to be
executed

Decode it: determine what is to be done

Execute it: issue appropriate command to ALU,
memory, and I/O controllers
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Machine Language Instructions

Can be decoded and executed by control unit

Parts of instructions

Operation code (op code)


Unique unsigned-integer code assigned to each
machine language operation
Address field(s)

Memory addresses of the values on which
operation will work
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Figure 5.14
Typical Machine Language Instruction Format
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Machine Language Instructions
(continued)

Operations of machine language

Data transfer


Move values to and from memory and registers
Arithmetic/logic

Perform ALU operations that produce numeric
values
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Machine Language Instructions
(continued)

Operations of machine language (continued)

Compares


Set bits of compare register to hold result
Branches

Jump to a new memory address to continue
processing
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Control Unit Registers And Circuits

Parts of control unit

Links to other subsystems

Instruction decoder circuit

Two special registers:

Program Counter (PC)


Stores the memory address of the next instruction to
be executed
Instruction Register (IR)

Stores the code for the current instruction
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Figure 5.16
Organization of the Control Unit Registers and Circuits
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Putting All the Pieces Together—the
Von Neumann Architecture

Subsystems connected by a bus

Bus: wires that permit data transfer among them

At this level, ignore the details of circuits that
perform these tasks: Abstraction!

Computer repeats fetch-decode-execute cycle
indefinitely
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Figure 5.18
The Organization
of a Von Neumann
Computer
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The Future: Non-Von Neumann
Architectures

Physical limitations on speed of Von Neumann
computers

Non-Von Neumann architectures explored to
bypass these limitations

Parallel computing architectures can provide
improvements: multiple operations occur at the
same time
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The Future: Non-Von Neumann
Architectures (continued)

SIMD architecture

Single instruction/Multiple data

Multiple processors running in parallel

All processors execute same operation at one
time

Each processor operates on its own data

Suitable for “vector” operations
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Figure 5.21
A SIMD Parallel Processing System
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Kent State ASsociative Computing
Model (ASC)
Associative Computer: A SIMD computer with a few
additional features supported in hardware.
 These additional features can be supported (less
efficiently) in traditional SIMDs in software.
 The name “associative” is due to its ability to locate
items in the memory of PEs by content rather than
location.
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Typical Data Structure for ASC Model
PE1
Make
Color
Year
Dodge
red
1994
PE2
PE3
IS
PE4
Price
Busyidle
1
1
0
0
Ford
blue
1996
1
1
Ford
white
1998
0
1
PE5
PE6
PE7
Model
On
lot
Subaru
red
1997
0
0
0
0
1
1
Make, Color – etc. are fields the programmer establishes
Various data types are supported. Some examples will show
string data, but they are not supported in the ASC simulator.
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The Associative Search
PE1
Make
Color
Year
Dodge
red
1994
Model
PE2
PE3
IS
PE4
Busyidle
1
1
0
0
Ford
blue
1996
1
1
Ford
white
1998
0
1
PE5
PE6
PE7
Price
On
lot
Subaru
red
1997
0
0
0
0
1
1
IS asks for all cars that are red and on the lot.
PE1 and PE7 respond by setting a mask bit in their PE.
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Modern SIMD-like Hardware
NVIDIA Tesla C870
GPU Computing
Processor
ClearSpeed Advance
X620 PCI-X Parallel
Accelerator
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The Future: Non-Von Neumann
Architectures (continued)

MIMD architecture

Multiple instruction/Multiple data

Multiple processors running in parallel

Each processor performs its own operations on its
own data

Processors communicate with each other
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Figure 5.22
Model of MIMD Parallel Processing
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Cluster Computing
Rack Mount cluster:
24 nodes with 1 gateway node
Total 4TB of hard disk space
http://www.tik.ee.ethz.ch/~ddosvax/cluster/
22 cluster nodes: Athlon XP "Barton"
•2.8 GHz 1 GB RAM,
•120 GB Hard disk
•CD-ROM Drive
•1 Gbit/s-Ethernet
One single gateway node: Athlon XP "Barton" 2.8 GHz
•1 GB RAM
• 2x 200GB Hard disk (200 GB RAID-1 mirrored)
http://www-cs.canisius.edu/facilities.shtml
•CDROM
•1 Gbit/s-Ethernet internal; 100 Mbit/s external.
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Quantum Computing


Online introduction for class reading
http://computer.howstuffworks.com/quantumcomputer.htm/printable
For a slightly more in-depth introduction
http://www.cs.caltech.edu/~westside/quantum-intro.html
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Summary of Level 2

Focus on how to design and build computer
systems

Chapter 4

Binary codes

Transistors

Gates

Circuits
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Summary of Level 2 (continued)

Chapter 5

Von Neumann architecture

Shortcomings of the sequential model of
computing

Parallel computers
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Summary




Computer organization examines different
subsystems of a computer: memory,
input/output, arithmetic/logic unit, and control
unit
Machine language gives codes for each
primitive instruction the computer can perform,
and its arguments
Von Neumann machine: sequential execution of
stored program
Parallel computers improve speed by doing
multiple tasks at one time
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