Transcript Marchioro_-_Zaragoza_2013_

State of the Art in Microelectronics
Miniaturization and Integration
Microelectronics for
Particle Detectors
A. Marchioro
CERN, Div. PH
1211 Geneva 23, Switzerland
Overview
Motivations: i.e. the talk’s message:
– Experiments require systems, not chips
Brief intro on technology perspectives
– History
– Technologies for SoC
– Advanced Devices for Billion transistor chips
Opportunities:
– SoCs for gas detectors
– SoCs for trackers
Conclusions
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MOTIVATIONS
-
History of mElectronics for HEP vs Commercial
Areas with potential for growth
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Microelectronics in HEP
1985 to 1995 - Generation 0 :
–
–
–
2u down to 1.0 u
Proofs of concept
First dedicated ASICs for strip detectors
»
–
Low-noise charge amplifiers
First simple digital chips
1995 to 2005 – Generation 1:
–
–
0.8um down to 130nm
Front-end ASICs with analog/digital pipelines
» First complex pixel chips
–
–
Radiation issues (a very hard problem!)
First monolithics (MAPS etc.)
2005 onwards:
–
–
–
130 nm and below
Complex SoC
Intelligent detectors
»
»
–
–
Capable of performing significant local processing
But the brain is in the electronics, sorry…
System optimized for (integration) cost
High density interconnect
»
1980
i286, 1.5 um, 130K tr., 6 MHz
1985
i386, 1.5 um, 275K tr., 16 MHz
1990
i486, 1.0 um, 1.2M tr., 25 MHz
1995
PentPro, 0.6 um, 5.5M tr., 200 MHz
2000
P4, 0.18 um, 42M tr., 1.5 GHz
2005
PentiumD, 65 nm, 291M tr., 3.2 GHz
2010
iCore, 32 nm, 1.2B tr., 3.8 GHz
2015
…
Intel Processors Timeline
Stacks of chips or hybrid chip-detectors
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Microelectronics in HEP
1985 to 1995 - Generation 0 :
–
–
–
2u down to 1.0 u
Proofs of concept
First dedicated ASICs for strip detectors
»
–
Low-noise charge amplifiers
First simple digital chips
1995 to 2005 – Generation 1:
–
–
0.8um down to 130nm
Front-end ASICs with analog/digital pipelines
» First complex pixel chips
–
–
Radiation issues (a very hard problem!)
First monolithics (MAPS etc.)
2005 onwards:
–
–
–
–
–
1985
Nokia Technophone 105,
analog, 5500gr,
1990
Cityman 100, analog, 500 gr
1995
1610, 2210, first GSM 900, 230 gr,
2000
3310, GSM, 130 gr
2005
8800, GMS, WAP, camera, 130 gr
2015
Capable of performing significant local processing
But the brain is in the electronics, sorry…
System optimized for (integration) cost
High density interconnect
»
Mobira Senator, analog, 9800 gr
2010
130 nm and below
Complex SoC
Intelligent detectors
»
»
1980
iPhone 3GS , 3G, WiFi, GB memories,
full OS, camera, email, video, …
iPhone 7 , 4G, WiFi, GB memories,
full OS, camera, email, video, …
Phones Timeline
Stacks of chips or hybrid chip-detectors
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System Complexity – ADSL Example
Interleaver
Convolutional
Encoders
Symbol
Mapping
IFFT
Cyclic
Prefix
Analog FE
CRC & RS
Encoders
CRC &
RS
Decoders
Deinterleaving
Viterbi
Decoder
Symbol
recovery
A/D
FFT
Equalizer
Prefix
Remove
Time
Domain
Equalizer
Amp
Adapter
D/A
FFT
POTS
Splitter
Amp
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Why do you need microelectronics?
Functionality
– Requirements for new (large) detectors can only be
fulfilled by Application Specific Ics
» Example: no way to buy a ready-made Tracker
RH
– No choice other than advanced or modified tech ASICs
– COTS not easily qualified for usage
Cost:
– HEP instrumentation has not made the transition to
“commodity” detectors, everything is hand-made, design
is for performance and not (really) for cost, systems are
not conceived for manufacturability, just for function
or/and performance
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Potential for improvements
FE:
Low
»
»
»
»
intrinsic speed or resolution of detectors is not expected to improve dramatically
FE circuits close to intrinsic noise margins
CMOS tech evolution is not going to improve analog (actually probably worse, see later)
Only 3D integration can change the game
A/D Conversion: Medium to Hih
» conversion energy is still being improved, new architectures introduced, digital helps.
Caveat: many companies make ADC IPs, do not design ADC, buy them!
Digital signal processing: High to very high
» Little or no “signal processing” is done today in HEP (shaper is analog)
» Some laudable attempt in the “Altro” project (pedestal correction, tail cancelation etc.)
» Much more to be done
Data Processing (i.e. Feature Extraction): Huge
» Little intelligence in chips: lots of raw (and meaningless!) data shipped out at the cost
embedded BW, power and of expensive links
» Trigger (i.e. pattern recognition) opportunities
» Feature extraction could easily be done now
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WHAT TO EXPECT FROM ADVANCES IN TECHNOLOGY
-
Advanced CMOS
A flavor of the problems for making nano-transistors
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How many more generations?
“The end of the planar FET is close, but perhaps one
or two generations can be added if newer transistors
can be made, for example the ‘FINFET’”
G. Moore, 2003
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From ITRS 2011
CMOS Technology Roadmap
There is no doubt that industry will be well ahead
of the requirements from the HEP community,
including HL-LHC, ILC etc.
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Technologies used in ISSCC papers
Trends 2007/2013
30.0%
2007
Percentage of papers
25.0%
2008
2009
20.0%
2010
2011
15.0%
2012
10.0%
2013
5.0%
0.0%
> 0.8
0.5
0.35 0.25 0.18 0.13
90
65
45-38 32-28 24-22 20-18 BCD
TriGate
Technology
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Some advanced devices
22 nm TriGate from Intel
Various sources
20 nm FDSOI from ST
28 nm planar from TSMC
32 nm SOI from IBM
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16 nm FINFET
Source: TSMC
16 nm
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©permission IEEE, C.-H. Jan et al.,A 22nm SoC Platform…, IEDM12-44,
… and still, devices behave very well
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Technology enablers
Lithography
– Solution: turn the problem to work to your advantage!
» Correct mask and process distortions by
synthesizing masks and not by introducing shorter
wavelength
– Double and multiple patterning
» Build images by superimposing patterns
New materials
– SOI wafers (reduce parasitic capacitances)
– Si-Ge and channel stress (enhance mobility)
– Gate oxide materials (need to avoid leakage
currents)
– Metal gates (avoid problem of poly depletion),
lower R
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© permission IEEE, S.H. Lo et al.,Quantum-Mechanical Modeling… IEEE JSSC 18,5, 1997
– OPC
from X. Wang et al.,
IEDM 2011,
from K. Bernstein et al.,
IBM J. Res. & Dev. Vol. 50 No. 4/5, 2006
Atomic Scale Variability
Atomistic view of dopants in 50nm transistor
Distribution of Vt on three generations of FinFETS, 20nm, 14nm, 10nm
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Some looming difficulties
Device variability
– transistors have atomic dimensions: dopants are in
“countable” number, oxides are few atomic layers thick
Slow lithography
– short wavelength powerful light sources are hard to make
Cost of new foundry
– Sub-20nm fab > 5B$
Design complexity
– number of devices (all must work, both functionally and
physically!)
– variability implies huge simulations
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IMPORTANT BENEFITS FROM NEW TECHNOLOGIES
130 and 65 nm and Radiation hardness
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Core 130nm NMOS transistors, normal layout
Effect on the leakage current
1.E-05
– Peak in leakage @ TID of 1-5Mrad
0.16/0.12
0.32/0.12
0.48/0.12
0.8/0.12
2/0.12
10/1
10/10
ELT
1.E-06
1.E-07
Ileak (A)
– Good recovery, strong indications
that ELT is not needed for regular
digital
1.E-08
1.E-09
1.E-10
1.E-11
1.E+05
pre-rad
1.E+06
1.E+07
1.E+08
Foundry B
1.E+09
annealing
1.E-05
1.E-05
1.E-06
1.E-06
1.E-07
1.E-07
Ileak (A)
Ileak (A)
TID (rad)
1.E-08
N_10_013
1.E-09
N_10_10
1.E-08
N_10_012
N_088_012
1.E-09
N_04_013
N_053_012
N_024_013
N_018_013
1.E-10
1.E-10
N_028_012
N_014_013
1.E-11
1.E+04
pre-rad
1.E+05
Foundry A
1.E+06
1.E+07
TID (rd)
1.E+08
N_016_012
1.E+09
1.E-11
1.E+04
pre-rad
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1.E+05
1.E+06
1.E+07
1.E+08
annealing
1.E+09
TID (rd)
Foundry C
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Core devices in 65nm, normal layout
10
0.03
Vth [V]
0.01
10
-10
Ileak [A]
0.02
ELT,148060 nm
12060 nm
24060 nm
36060 nm
48060 nm
60060 nm
100060 nm
101 mm
1010 mm
-9
0
-0.01
10
-11
ELT
12060nm
24060nm
36060nm
48060nm
60060nm
100060nm
101mm
1010mm
From S. Bonacini et al, TWEPP 2011
-0.02
-0.03
5
10
10
6
7
10
TID [rad]
10
8
10
9
10
-12
10
4
10
–
Some rebound effect visible for narrow devices
in 130nm: was 150mV
At high doses Vth shift is positive for wide devices,
negative for narrow devices
–
10
6
10
7
10
8
10
TID [rad]
Up to ~20mV shift for 200 Mrad
–
5
STI edge oxide traps considerable charge (RINCE)
Less than 10× increase in leakage
for wide devices (W > 360nm)
Narrow devices have up to 2.5
orders of magnitude increase
Subtreshold slope does not change significantly
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OTHER BENEFITS FROM NEW TECHNOLOGIES
Size, functionality and features
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Example of 130 nm density potential
Same scale
12 bit PIC® compatible
microprocessor core
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IO cell
23
Comparison of ARM® compatible processor from University of Edinburgh,
see: http://groups.inf.ed.ac.uk/pasta/hw_encore.html
Any idea for embedded FE processing?
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Interfacing to the “standard” world
USB 2.0 OTG
– ~ 20-60K Gates [1]
Ethernet 10-100-1000 MAC
– 20,560 gates [2]
Notice that:
– 1 mm2 in 130 nm contains ~ 200K gates
– 1 mm2 in 65 nm contains ~ 800K gates
…and
– Production cost of 1 mm2 in 130nm < 0.1 $
– Production cost of 1 mm2 in 65 nm < 0.15 $
______________________________________________________________
[1] http://www.faraday-tech.com/techDocument/FOTG200_ProdBrief_v1.2.pdf
[2] http://opencores.org/project,ethernet_tri_mode
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Further advantages at 130 nm and below
More process options useful for detector
integration
– More metal levels:
» shielding, power distribution (pixel chips are often
accessible on one side only), routability i.e. density
– More device types
» Many optimized Vt MOSFETs, higher capacitor
density, inductors, varicap, resistor types, fuses
– More substrate options
» NMOS p-well is almost universally available
» substrate isolation for good noise isolation properties
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65nm
Analog features:
–
–
–
–
Device intrinsic gain (= gm * r0): worse than 130nm
Device max frequency: ~ 2x better than 130nm
Matching: better than 130nm
Intrinsic noise: about same as 130 nm or slightly better
Digital features:
– density:
» 4 x 130nm (even with RT devices)
– speed:
» ~ 2x 130 nm (depending on flavor)
– power:
» ½ to ¼ than 130 nm
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FM =
Advances in ADCs
Power
Freq * 2 ^ ENOB
ENOB =
(SNDR -1.76)
6.02
1.E+07
1.E+06
P/fsnyq [pJ]
Courtesy of Prof. B. Murmann, Stanford University
1.E+05
1.E+04
1.E+03
1.E+02
ISSCC 2013
VLSI 2012
ISSCC 1997-2012
VLSI 1997-2011
FOMW=10fJ/conv-step
FOMS=170dB
1.E+01
1.E+00
1.E-01
10
20
30
40
50
60
70
80
90
100 110 120
SNDR @ Nyquist [dB]
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Source: TSMC financial report
Obsolescence?
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OPPORTUNITIES:
- Chips for gas detectors
- Chips for trackers
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Figure 5.1 in B. Grube’s Thesis “The Trigger Control System
and the Common GEM and Silicon Readout for the COMPASS Experiment”
Chips for gas detectors
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Source L. Musa, CERN-PH
First complex chip: the “Altro”
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Signal Processing in Altro
HIGH MULTIPLICITY COSMIC RAYS
Occupancy ~ 50%
• raw samples
• after signal processing
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Source T. Alt, L. Musa, CERN-PH
More cluster signal processing
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“Image” processing on chip
“Image” processing well possible with
current technologies
– Cluster reduction on FE chips
– Intelligent “zero suppression”
» Always collect “halos” around channels above
threshold
– Charge summing for adjacent pixels
» See Medipix3 approach!
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Charge summing in Medipix3
The winner takes all
Charge
is is
• Full
charge
summed in
assigned
to every
single4hit
pixel cluster on an
event-by-event
basis
55µm
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Measurements (60keV, 110mm pitch, 2mm CdTe)
(Energy spectra measurements with
Medipix3RX and CdTe: T. Koenig talk
(Detectors and simulations 2))
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Chips for Trackers
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Local feature extraction for trackers
Level-1 data require local rejection of low-pT tracks
– To reduce the data volume, and simplify track finding @ Level-1
» Threshold of ~ 1÷2 GeV data reduction of about one order of
magnitude
Design modules with pT discrimination (“pT modules”)
– Correlate signals in two closely-spaced sensors
» Exploit the strong magnetic field of CMS
Level-1 “stubs” are processed in the back-end
– Form Level-1 tracks, pT > 2÷2.5 GeV
“stub”
» To be used to improve different
trigger channels
m
m
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r
z
F
m
39
Simplified cross-section
Short Strip ASIC
~ 2 mm
Strip sensor
~ 48 mm
Cooling
R
Substrate
Pixel Sensor
MacroPixel ASIC
Z
• One layer of strips + One layer of Strixels
• r-F resolution: 100 mm
• Z resolution: 1.5 mm
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@ L1
Clocks
Event
Formatter
Strip
Event
Store
Wide cluster
elimination
Strip
Triggering functionality
CLK Generation
& Cntrl
Config Regs
Windowed
pT coincidence
FE
Traditional data path
MPixel
Event
Store
Position
decoder
from MPixel column
MPixel ASIC dataflow
Intf to GBT
Link
Trigger Logic
@ each BX
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MPA: Trigger (stub) generation
Retime[1:0]
<512>
<512>
<128>
<8>
<128>
<140>
StripCluster
Elimination
& Centroids
<140>
F
Shift
<128>
(2 of 64 bits)
CentroidsRetime
Minus
<512>
LeftRightOut
<128>
Coincidence
Z
Priority
Encoder
<128>
PixelPipeOut[511:0]
<8>
<136>
PixCluster
Elimin &
Centroids
PixelHit
Retiming
<128>
PixelOredHitReg
<8>
PixelPipeReg1
Column
OR-ing
StripHitReg
<2048>
PixelHitReg
LeftRightIn
<128>
<8>
Plus
PhiShift[]
ClusterCut[3:0]
MatchMask[1:5]
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Retime
Strip[1:0]
42
Conclusions
Development is limited by (lack of) ideas,
not by technology
– … and not even by the “cost” of adv tech
The HEP community has much to learn,
(and to profit from) adopting standards, IP
sharing, and avoiding NIH attitudes
Detectors and microelectronics should be
developed in parallel
– much to be expected from jointly conceived
SoC for detectors
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Spares
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Core 130nm NMOS transistors, enclosed layout
NMOS ELT min/0.12
1.00E-03
1.00E-04
1.00E-06
Pre-rad
Id (A)
G
1.00E-05
1.00E-07
3Mrad
1.00E-08
136Mrad
2d HT ann
1.00E-09
1.00E-10
1.00E-11
1.00E-12
-0.2
0.3
0.8
1.3
Vg (V)
PMOS ELT min/012
S
1.E-04
1.E-05
1.E-06
Id (A)
D
1.E-03
1.E-07
pre-rad
3 Mrd
40 Mrd
1.E-08
1.E-09
1.E-10
1.E-11
1.E-12
-0.2
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0.3
0.8
Vg (V)
1.3
45
A. Gianoli et al., The NA48 LKr calorimeter readout electronics, RTC 1999
Halo Energy recovery for trigger in NA48
ETot =
å E +åE
j
>Thres
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Neigh
46
k
Hybrid strip-pixel Module Concept
Z
f
•
•
Use one layer of short strip: ~24 mm
and one layer of ~1.5 mm long macro-pixels
In the pixelated layer, perform the OR of the pixels in the Z direction and use it as
single strip in Z
Coincidence of the two layers provides pT cut
Pixel position provides Z coordinate
•
Thickness: two sensors + Pixel strip RO + cooling interposer + hybrid sideways
•
•
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