Transcript AVR Microcontroller

AVR MICROCONTROLLER
SAMARTH COLLEGE OF ENGINEERING &TECHNOLOLOGY
DEPARTMENT OF ELECTRONIC & COMMUNICATION ENGINEERING
5 th sem (E&C)
Guided By:Prof. HIMANSHU PRAJAPATI
Subject Code [2151001]
Prepared By:1.PATEL MAYURKUMAR D.
2.CHAUHAN HARDIKSINH R.
3. PATEL SRUSHTI P.
4. ACHARYA SUNITA S.
(120880111003)
(130880111001)
(130880111005)
(130880111006)
Topics
 Introduction to AVRs
 AVR Architecture & Instruction Set
 Focus on Atmega128 AVR
 AVR Programming
Microcontroller
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Microcontrollers are important part of
Embedded systems
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To understand Structure & working of
Microcontrollers
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For Designing good Embedded system
complete understanding microcontrollers
required
Microcontroller
• Integrated chip that typically contains integrated CPU, memory (RAM ROM), I/O
ports on a single Chip.
•System on a single Chip
•Designed to execute a specific task to control a single system
•Smaller & Specified (design cost)
•Differs from Microprocessor general-purpose chip
•Used to design multi purpose computers or devices
•Require Multiple chips to to handle various tasks
AVR Microcontroller
 AVR stand for?
• Advanced Virtual RISC,the founders are Alf Egil Bogen Vegard Wollan
RISC
•AVR architecture was conceived by two students at Norwegian Institute
of Technology (NTH)[1] and further refined and developed at Atmel
Norway, the Atmel company founded by the two chip architects.
RISC Microcontroller
Reduced Introduction Set Computer
Till 1980 Trend was to build increasingly complex CPUs with
complex set of instructions like (CISC)
(RISC)
Instruction execute in single cycle
“Architecture which reduces the chip complexity by simpler
processing instructions”.
RISC architecture CPUs capable of executing only a very limited
(simple) set of instructions.
RISC Microcontroller
Reduced Instruction Set Computers Advantages
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Fast Execution of Instructions due to simple instructions
for CPU.
RISC chips require fewer transistors, which makes them
cheaper to design and produce.
Emphasis on software
Single-clock,reduced instruction only
Register to register: “LOAD" and "STORE“
are independent instructions
Spends more transistors on memory registers
AVR Microcontroller
The AVR is a Harvard architecture CPU.
Harvard Architecture
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Computer architectures that used physically
separate storage and signal pathways for their
instructions and data.
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CPU can read both an instruction and data from
memory at the same time that makes it faster.
von Neumann architecture
CPU can Read an instruction or data from/to the memory.
Read, Write can`t occur at the same time due to same
memory and signal pathway for data and instructions.
AVR Microcontroller
Harvard Architecture
Harvard Architecture diagram
AVR Microcontroller
A series of 8-bit RISC microcontrollers from Atmel.
All AVR microcontrollers share same instruction set and a
basic CPU (Harvard) architecture.
It has 32 8-Bit general purpose registers.
Mostly instruction Execute in Single clock cycle. Which
makes it faster among 8 bit microcontrollers.
AVR was designed for efficient execution of compiled C
code.
AVR Microcontroller
AVR is a family of 8-bit microntrollers with a large range of
variants differing in:
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size of program-memory (flash)
size of EEPROM memory
number of I/O pins
number of on-chip features such as uart and adc
Smallest microconroller is the ATTiny11 with 1k flash ROM,
no RAM and 6 I/O pins.
Large such as the ATMEGA128 with 128k flash, 4KB RAM,
53 I/O pins and lots of on-chip features.
AVR Architecture
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Registers
Instruction Set
I/O ports
Memory (flash & RAM & ROM)
CPU
AVR Architecture
 Registers:
Two types of registers
GERNEL purpose & SPECIAL purpose registers
 GERNEL purpose
32 general purpose registers having storage capacity of 8-Bits
Named as R0,R1,R2 to R31.
Register 0 to 15 & 16 to 31 are different.
Can store both Data & Addresses.
 SPECIAL purpose: Three registers
Program counter
Stack Pointer
Status Register
AVR Architecture
Pointer Register
Three 16-bit address registers pairs of registers 26 to 31
have extra meaning in AVR assembly.
X (r27:r26), y (r29:r28), z (r31:r30).
pointer
Sequence
X
Read/Write from address X,
don't change the pointer
AVR Architecture
status register (SREG) that contains
It is 8-bit long each bit has a different meaning.
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T
H
S
V
N
Z
C
I: Global Interrupt Enable/Disable Flag, SREG7
T: Transfer bit used by BLD and BST instructions, SREG6
H: Half Carry Flag, SREG5
S: For signed tests Instruction Set, SREG4
V: Two's complement overflow indicator, SREG3
N: Negative Flag, SREG2
Z: Zero Flag, SREG1
C: Carry Flag, SREG0
AVR
Register Architecture
AVR Architecture
Memory:
There are two separate
memories
Program Memory (Flask
Memory)
Data Memory
AVR
AT90S2313 instruction Architecture
AVR Instruction SET
118 Powerful Instructions – Most Single Clock Cycle Execution
All arithmetic operations are done on registers R0 - R31
Mostly instructions take one cycle for execution
ADD Rd,Rr
Rd: Destination (and source) register in the Register File
Rr: Source register in the Register File
AVR
AT90S2313 instruction Architecture
Instruction add R23, R11
Be encoded as the 16-bit opcode 0x0EEB.
Bit pattern : 0000 1110 1110 1011
Three components.
5 red bits 00011 distinguish this as an add instruction.
5 blue bits 10111 indicates register 23 is the first
operand register.
The 5 green bits 01011 indicates register 11 is the
second operand register.
All add Rd, Rr instructions follow this pattern.
AVR
AT90S2313 I/O Pins
Port B is an 8-bit bi-directional I/O port.
Three I/O memory address locations are allocated for the Port B,
Data Register (Read/Write) PORTB, ($38),
Data Direction Register (Read/Write) DDRB, ($37)
PortB Input Pins (read-only, )– PINB, ($36).
All port pins have individually selectable pull-up resistors.
AVR
AT90S2313 I/O Pins
Port B Data Register – PORTB
Port B Data Direction Register– DDRB
Port B Input Pins Address –PINB
AVR
AT90S2313 I/O Pins
Three I/O memory address locations are allocated for the Port D:
Data Register (read/write)– PORTD, $12($32),
Data Direction Register (read/write)– DDRD, $11($31)
Port D Input Pins(read-only) – PIND, $10($30).
AVR
AT90S2313 I/O Pins
Port B Data Register – PORTB
Port B Data Direction Register– DDRB
Port B Input Pins Address –PINB
AVR
AT90S2313 CPU
CPU
– Up to 10 MIPS Throughput at 10 MHz
The AVR is a Harvard architecture CPU, The AVR is a Harvard
architecture CPU,
Program Memory Is separated from data Memory
Program memory is accessed with a single level pipelining
(Fetch & execute).
AVR Studio
Integrated Development Environment (IDE) for writing
and debugging AVR applications for windows
environments.
AVR Studio provides a project management tool,
source file editor, chip simulator and In-circuit
emulator interface for the powerful AVR 8-bit RISC
family of microcontrollers.
Download site: AVR Studio 4
http://www.atmel.com/dyn/products
THANKS