Transcript Wednesday 03 February 2010 Applications of intelligent detectors I

WIT2010 Workshop on Intelligent Trackers
Wednesday 03 February 2010 - Friday 05 February 2010
Lawrence Berkeley National Lab
Organized by C. Haber and M. Garcia-Sciveres
Wednesday 03 February 2010
Applications of intelligent detectors I
Applications of intelligent detectors II
Coupled layer and monolithic architectures I
Hartmut
Hartmut
Phil
Thursday 04 February 2010
Development of specific components, for example low mass interposers
Coupled layer and monolithic architectures II
Phil
Electronic circuits (3D and conventional)
Phil
Friday 05 February 2010
High speed communication
System integration
Tours of LBNL facilities
http://indico.cern.ch/conferenceDisplay.py?confId=68677
Hartmut
Applications of intelligent detectors I - - Convener: Haber, Carl
Guessing the geometric features of a particle trajectory in a magnetic field by measuring one point
and its tangent.
Prof. PARRINI, Giuliano
Concepts and validations of a pT based tracker trigger using single and double sensors strip
modules using CMS data
Dr. PALLA, Fabrizio
Intelligent Trackers as L1 Trigger providers for the SLHC
MANNELLI, Marcello
A First Level Track Trigger for ATLAS at Super-LHC
SCHMITT, Sebastian
Triggering performance of stacked pixel layers for the SLHC CMS tracker
PESARESI, Mark
Applications of intelligent detectors II - Convener: Allport, Phil
I-ImaS: Intelligent Imaging Sensor - application to intelligent X-ray imaging Dr. GRIFFITHS, Jennifer
Pixel Imaging Mass Spectrometry with fast pixel detectors
Dr. NOMEROTSKI, Andrei
Data Compression and LVL1 track triggering by means of Digital Signal Processing in
GridPix/Gossip FE pixel chips
VAN DER GRAAF, Harry
Track finding with radially pointing scintillating fibers
Prof. STUART, David
Coupled layer and monolithic architectures I - - Convener: Palla, Fabrizio
Design and development of a micro-strip stacked module prototype to measure flying particles
direction
Dr. MESSINEO, Alberto
2-D PT module concept for the sLHC CMS tracker
HALL, Geoff
System Concepts for Doublet Tracking Layers
Dr. HABER, Carl
Coupled layer and monolithic architectures II - - Convener: Hall, Geoff
Architecture of a module with transverse momentum discrimination for the CMS Tracker Upgrade
Mr. MARCHIORO, Alessandro
Vectors and Submicron Precision: Redundancy and 3D Stacking in Silicon Pixel Detectors
Dr. HEIJNE, Erik
A high efficiency readout architecture for a large matrix of pixels.
Dr. GIORGI, Filippo Maria
Development of specific components, for example low mass interposers - Convener: Brenner, Richard
Development of Interconnect Technologies for HEP Applications
Development of Silicon Interposers
A Silicon and Carbon Foam Low Mass Interposer
TRIPATHI, Mani
Prof. ALEXANDER, James
GARCIA-SCIVERES, Maurice
Electronic circuits (3D and conventional) - - Convener: Marchioro, Alessandro
Application of Vertically Integrated Electronics to Intelligent Trackers
Dr. LIPTON, Ronald
Fast Readout Logic Interfacing a 256-Pixel Matrix of a Dual-Layer 3D Device
GABRIELLI, Alessandro
Present and future inter pixel communication architectures in Timepix/Medipix derived read out
chips
LLOPART CUDIE, Xavier
Towards a high performance vertex detector based on 3D integration of Deep N-Well
MAPS
RE, Valerio
High speed communication - - Conveners: Mr. Demarteau, Marcel
Architecture of a Level 1 Track Trigger for the CMS Experiment
Prof. HEINTZ, Ulrich
FF-LYNX: protocol and interfaces for the control and readout of future silicon detectors
MAGAZZU, Guido
Wireless data transfer at 60 GHz
Dr. BRENNER, Richard
New Optical Technology for Low Mass Intelligent Trigger and Readout UNDERWOOD, David
Ultra low power consumption 10.7 Gb/s transmission over 2 km single mode fiber optics link
Dr. JANNER, Davide
System integration - - Conveners: Garcia-Sciveres, Maurice
The design of stable, low-mass support and cooling structures
Dr. COOPER, William
DC-DC Conversion Powering Schemes for the CMS Tracker at Super-LHC Dr. KLEIN, Katja
Light prototype support using microchannel technology as high efficiency system for silicon pixel
detector cooling .
Mr. BOSI, filippo
Tours of LBNL facilities - Various locations (15:45-17:00)
Applications of intelligent detectors I
Mostly Tracking at LHC Upgrade Detector: Vectorizing inside of large detector
1) L1 Trigger
(does CMS really need it?),
need a factor 40 - 400 from L0 to L1
2) Track finding
Optimizing 1) and 2) most likely results in a different detector layout
2 methods, which could /might have to be combined:
a) Cluster size: can get pt measurement in a single plane:
ToP = Thickness over Pitch, sensitive to Threshold (2-4 sigma)
b) Combine stubs into tracklets from stack of detector doublets
PT Module with large pixels (Hall, Machioro)
• Assumed radial location ~25-45cm
allows to cover full CMS h range, with only barrel assembly
• Two double layers with ~2 mm radial separation, separated by ~ 4cm
• Pixel size ~100µm x 2.5mm defined by approximate projection of luminous region at R ~25cm
• Expected occupancy at R = 25cm ~0.5% @ 1035 so average <1 hit in column which may allow transfer to
edge
What about ATLAS?
(Concentrate on “region of interest” (no presentation))
One speaker proposes to send out all data and make trigger decision in one
micro second for L1 using look-up tables!
Example: Vectorizing in Track finding: Fast, high precision, low noise
Same method is being used by J. Nielsen et al
on the ATLAS Upgrade Silicon tracker.
A pt cut is trivially applied by cutting on the slope
Applications of intelligent detectors II:
Very different ideas to exploit existing ASICs or technologies: MAPS
On-line Imaging planning in X-ray radiography
On-line Mass spectroscopy
L1 Trigger with GridPix
L1 triggering with radial fibers
I-ImaS concept
• Use data gleaned
locally to intelligently
modify local exposure
• Dual line-scan system
X-ray tube
Primary slot collimator
– Scout image
– Intelligent image
Linear
translation
Patient here
Detector slot
collimator
Sensor
Ion Imaging
 Fix a mass peak
 Measure full scattering
distribution of fragment ions
 Velocity maping
 Different fragmentation
processes give the ions
specific speed and angular
distributions
Ion
optics
Velocity mapping
S atom ion images for OCS
photodissociation at 248nm
Velocity Mapped PImMS (1)
CH3S2CH3
• 2007-2008: Proof of concept experiment successfully
performed on dimethyldisulfide (DMDS)3
• Ionization and fragmentation performed with a polarized
laser, data recorded with DALSA camera.
3: M. Brouard, E.K. Campbell, A.J. Johnsen, C. Vallance, W.H. Yuen, and A. Nomerotski, Rev. Sci. Instrum. 79, 123115, (2008)
projected track length
is measure for momentum:
- directly available (LVL1)
- at no (extra) cost (mass, power)
- at larger R: gas drift gap ~20 mm
~ 12 BXs
Requires fast on-pixel chip processing
We are using 130 nm tech.
What about 45 nm tech?
LVL1 trigger from GOSSIP inner tracker
Length of projected track
is direct measure for momentum
Use SiPMT, ~$20/pixel
“Cost:
crazy
by
several
orders
of
magnitude!”
Development of specific components, for example low mass interposers - Convener: Brenner, Richard
Development of Interconnect Technologies for HEP Applications
Development of Silicon Interposers
TRIPATHI, Mani
Prof. ALEXANDER, James
A Silicon and Carbon Foam Low Mass Interposer
GARCIA-SCIVERES, Maurice
Overview: nothing new? Many commercial interconnect methods (bump bonding
and many cottage indutries)
Work with commercial outfits: slow progress in AS3DI
(application specific 3D interconnects)
In-house 3D: goes only so far
Interesting alternative: use Si-C foam sandwiches.
Many avenues explored in parallel in CMS
pT modules
Vertically Integrated Modules
pixel
bump bond
Interposer with vias
Preamp/correlator
Conventional technology
3D technology
Carbon Foam Technologies (LBL)
Interconnects only
Interconnects + Hybrids
WIT2010 Workshop on Intelligent Trackers
Wednesday 03 February 2010 - Friday 05 February 2010
Lawrence Berkeley National Lab
Organized by C. Haber and M. Garcia-Sciveres
Wednesday 03 February 2010
Applications of intelligent detectors I
Applications of intelligent detectors II
Coupled layer and monolithic architectures I
Hartmut
Hartmut
Phil
Thursday 04 February 2010
Development of specific components, for example low mass interposers
Coupled layer and monolithic architectures II
Phil
Electronic circuits (3D and conventional)
Phil
Friday 05 February 2010
High speed communication
System integration
Tours of LBNL facilities
Harry
Harry
Hartmut
User of Track Information in the Level-1 Trigger
Requirements for Local Occupancy Reduction
•
Cannot possibly transfer all Tracker data at 40MHz !
•
Crossing Frequency / Event Read-Out ~ 40MHz / 100kHz ~ 1 / 400
– L1 Data reduction by a factor of 10 ~ 100 is required
•
•
For L1 Trigger propose to transfer only hits from tracks with
Pt > ~ 2 GeV
– The aim is to provide useful Isolation information
– Tracks with Pt > ~ 2 Gev are less than 1% of the Tracks inside acceptance
– This corresponds to the maximum plausibly manageable L1 data rate
•
In addition, must provide means of rapidly & reliably identifying high
Pt (isolated) tracks ( Pt > 10 ~ 25 GeV)
February 2010
Intelligent Trackers as L1 Trigger Providers for
the SLHC
Marcello Mannelli
The Basic Idea
Track stub reconstructed which, given the known location (at least in the r-φ
plane) of the interaction point, allows the track pT to be estimated
Basic Paired Module Concept
• Compare binary pattern of hit pixels on upper and
lower sensors Pass
Fail
High pT tracks can be
identified if hits lie
Upper Sensor
within a search window
in R-f (rows) in second
~200μm layer
R
1-2 mm
~100μm
f (rows)
Lower Sensor
f
~2.5mm
Sensor separation and
search window determines
pT cut
z (columns)
WIT 2010
Geoff Hall
27
Early results for a Stack of closely spaced
sensors: pitch ~ 100um*2.4mm (M. Pesaresi)
High rejection factors possible
Mark Pesaresi
February 2010
Much Sharper Threshold
For Low Threshold Value
Intelligent Trackers as L1 Trigger Providers for
the SLHC
Local Occupancy Reduction
a Hierarchical scheme with Double Stacks
•
Local Information Gathering, and Processing Hierarchy
Collect hits
from each sensor
& match into Stubs
~2mm
Collect Stubs
from each sensor doublet
& match into Tracklets
~40mm
•Within a Stacked-Sensor Module
Collect hits
from each sensor
& match into Stubs
–Collect Hits from each Sensor
–Match into Stubs& Reject Stubsfrom Very low Pt Tracks: Pt < ~ 2GeV
–Nb one datum / Hit Pair
•Within a Double Stack
–Collect Stubs from each Sensor Doublet Module
–Match into Tracklets
•Combine with other layers, and use to provide High Pt & Isolation L1
Track Trigger Primitives
February 2010
Intelligent Trackers as L1 Trigger Providers for
the SLHC
Early results for a pair of Double Stacks spaced
~ 10cm apart (M. Pesaresi)
Good discrimination
up to Pt ~ 20 GeV
Mark Pesaresi
February 2010
Intelligent Trackers as L1 Trigger Providers for
the SLHC
Possible Tracker Layouts
Incorporating Stacked Module Layers
•
Several potential layouts for an SLHC Outer Tracker are under study
– Want to increase granularity as well as minimize material in future tracker
– Need to understand how many triggering layers (in red), and where they need to be
located in order to provide adequate triggering capability
•
Here focus on the Long Barrel Straw Man as it is the most thought
provoking
Minimal Hybrid Layout
February 2010
Long Barrel Straw-Man
Intelligent Trackers as L1 Trigger Providers for
the SLHC
Schematic of PT module
• Transfer hits to both edges –with minimal power – for comparison
logic
Module 25.6mm x 80mm
– also store hits on pixel for L1 readout 256 x 32 sub-units = 8192 channels
Correlator
Data out
Occupancy ~ 0.5% => 40 hit pixels
PT reduction ≈ 20
=> 2 hit channels/BX
104
2
128 xx100µm
12.8mm
x
2x2.5mm
data
2 x 2.5mm
Geoff Hall
Correlator
WIT 2010
32
• Two micro-strip sensors
– Good performance for:
•
•
•
top sensor
Another Concept
P.A.
Track path length measurement
Simple Logic Correlation in space
Track direction of Flight
Hybrid
S-APV
Wire-bonding
Ideas by R. Horisberger
spacer
sensors
Level 1 w-bonds Level 2
Level 1 w-bonds Level 2
GND bonds
ATLAS Stave: Modules Glued to either side
of Substrate with
embedded Cooling
Glue
Glue
1.2m
Possible ATLAS Double Layer
Concept to use Stave but with both sides
as axial strip orientation and have inner
3 strip layers as trigger layers
Digital chip on hybrid
Fine pitch
interconnect
Bus cable
Sensor ~10 x 10 cm
Analog chip on hybrid
Carl Haber
Separate FE Functionality (Ampl,
Discr) from Digital Processing
Split the readout chip and use embedded fine pitch interconnection
ABCn
Binary readout
Digital chip on hybrid x5
top
Bus cable
pipeline
bottom
n
Wrap around
n+1
pre-amp disc
Sensor ~10 x 10 cm
Fine pitch
interconnect
Wrap
around
Analog chip on hybrid x10
Analog chip
trigger
output
Digital chip
Possible Implementations
Double Layer
Pixel Modules:
3D ASIC Technology
• A 3D chip is generally referred to as a chip
comprised of 2 or more layers of active
semiconductor devices that have been
thinned, bonded and interconnected to
form a “monolithic” circuit.
• Often the layers (sometimes called tiers)
are fabricated in different processes.
• Industry is moving toward 3D to improve
circuit performance.
– Reduce R, L, C for higher speed
– Reduce chip I/O pads
– Provide increased functionality
– Reduce interconnect power and crosstalk
• This is a major direction for the
semiconductor industry.
IBM/Cornell/UCSB Study
– vision of 22 nm 10Tflop
3D chip (2018)