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Electronic Counters
Abstract
Electronic counters come in two flavors: asynchronous and synchronous. Asynchronous
counter encode a count sequence by directly connecting flip-flops and allowing the clockpulse to ripple through the cascade. Synchronous counters use a common clock and logic
between flip-flops to encode the count sequence. Asynchronous counters are simpler
because they do not require logic gates, but any latency will scale linearly with respect to
the number of bits. Synchronous counters are more complex but constrain the latency. If
the cumulative latency is greater than the maximum allowable cycle time, then a
synchronous architecture is preferable. If the application is not sensitive to false errors
produced by latency, however, an asynchronous counter alone or with over-clocking (in
the event that cumulative latency is greater than the cycle time) may be feasible.
Alternatively filters, such as a strobing circuit, can be used to remove erroneous outputs
caused by latency from the output.
Flip Flop
Output
Systems : Counters
Memory devices : Flip flops
Input
Logic gates
Output’
Transistors
And diodes
Solid State
Physics
-
Input 2
Flip
Flop
N
+
Clock
P
Electronic counter
Addressable
I/O signals
Wires
Memory device
Flip flop
Counter
Architecture
Asynchronous
Synchronous
A bit is a two-state object,
such as a flip-flop.
Electronic flip-flop
State
0
1
A collection of n bits can encode 2^n
information levels (states).
State
0
All possible
information levels for
three bits
1
0
000 001 010 011 100 101 110 111
Each information level can
represent a number.
State
0
All possible
information levels for
three bits
0
1
000 001 010 011 100 101 110 111
1
2
3
4
5
6
7
8
Bits oscillating with proportional
frequencies encode count sequence.
000
1
Bit
1
Bit
2
Bit
3
001
2
010
3
011
4
100
5
101
6
110
7
111
8
Counter system architecture
connects bits (JK flip-flops) to
produce this frequency pattern.
Bit
1
Bit
2
Bit
3
Asynchronous
Couple two two bits so that inverse
output from bit 1 is trigger for bit 2.
Output 1
“Trigger”
Bit 1
“Trigger”
Inverter
Output 2
Bit 2
Bit 1 output and inverted output
Trigger 1
Output 1
Output 1
Inverted
Bit 1 inverse output serves as clock
for bit 2. Triggers state change at
positive going transitions.
Output 1
Inverted
Trigger 2
Output 2
2 outputs of proportional frequency
produce the count sequence
Output 1
Output 2
00
01
10
11
1
2
3
4
But if there is a delay between
command to toggle and response …
Latency
JK Flip-Flop
“Trigger”
“Trigger”
AND
Toggle:
Change State
“Enable”
Bit
State
Delay, D
… latency scales linearly wrt # of bits
Ideal
Clock 1
Observed
D
Bit 1
Clock 2
D
Bit 2
Accumulated latency = n*d, for counter of n bits
And results in an erroneous count.
Ideal
Observed
D
Clock 1
Bit 1
D
Clock 2
Bit 2
01 (2)
10 (3)
01
01
00 (1)
10
But if accumulated delay occurs
before clock returns to low state …
Clock 1
Accumulated delay = (n-1)*d
Clock
n
Bit n
Accumulated delay = (n)*d
… let error ripple through the system when clock is high,
then read output when the clock is low.
“Strobing” circuit
Clock 1
Low enable
is True
Bit 1
Clock 2
Bit 2
01
10
Then read bits to produce correct output
Problem: delay limits clock speed …
Clock 1
Clock frequency must be set allow
cumulative delay to ripple through
cascade of bits during the high level of the
trigger.
Thus, the length of ½ cycle > length of
cumulative delay
Clock
n
Bit n
Cumulative delay = (n)*d
In applications where false outputs
from propagation delay produces
errors and where speed is important,
synchronous counter that avoids
“rippling” is preferable.
Synchronous
Couple enable to logic gate that
processes output from prior bits :
when all prior bits are high, then 1
passed to bit and output toggles.
JK Flip-Flop
“Trigger”
AND
Prior
Bits
“Inputs”
Toggle
Output
Synchronous counter: each bit holds
its state until all preceding bits are
high and positive clock pulse.
Q1
High
Clock
Q2
1
Q3
And
2
3
Clock
Q1
Q2
Q3
0
1
0
0
1
1
0
1
0
0
1
1
0
1
000 001 010 011 100 101 110 111
1
2
3
4
5
6
7
8
Bits flip simultaneously, with same latency :
no false outputs
Clock
Bit 4 trigger
0
1
D: latency of flip-flop
Bit 1
Bit 2
Bit 4 enable:
Logic gate
inputs
Bit 3
Bit 4
Bit 4 state
1
1
1
1
1
1
0
1
Time 1
Time 2: Flip
Compare synchronous to asynchronous …
Clock
D
Grows to 4*D
Bit 1
Bit 2
Bit 3
Bit 4
Latency for synchronous fixed and no false outputs but is synchronous is 4*D by 4th flipflop, necessitating measures (“strobing circuit”) to prevent errors and thus limiting speed.
Knowing …
1. Cumulative latency
for asynchronous
counter
Clock
2. Minimum acceptable clock speed
Clock
Maximum acceptable
cycle time
Clock n
Latency
Bit n
Decision …
Is cumulative
latency > maximum
cycle time?
Yes
No
Synchronous
Architecture
Do false outputs
resulting from
latency cause
errors?
No
Asynchronous
Architecture
Yes
Is cumulative
latency < ½
maximum cycle
time?
No
Yes
With strobing circuit to “block”
output during high level in clock cycle.