Transcript Programmable ASICs

Chapter 4
Programmable ASICs
Application-Specific Integrated Circuits
Michael John Sebastian Smith
Addison Wesley, 1997
EGRE 427 Advanced Digital Design
Figures from Application-Specific Integrated Circuits, Michael John Sebastian
Smith, Addison Wesley, 1997
Programmable ASICs
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Two basic types of programmable ASICs
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Programmable Logic Device (PLD) - first developed as small
programmable devices that can replace a handful of TTL parts
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Field Programmable Gate Array (FPGA) - more complex devices that
can hold up to 100K gate equivalents or more
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least complex ones are a simple AND/OR PLA with latches on the outputs
and feedback paths to the inputs of the array
some implemented as symmetrical arrays of simple logic devices
others include more complex and specialized logic blocks
An FPGA (or PLD) is an IC that is fabricated with some connections
missing
The user (designer) creates a design to be placed on the FPGA
using design entry and simulation
Automatic tools create a string of bits (a configuration file) describing
the extra connections necessary to program the FPGA to perform
the required function
A device programmer is then (usually) used to load the configuration
file into the FPGA
EGRE 427 Advanced Digital Design
Figures from Application-Specific Integrated Circuits, Michael John Sebastian
Smith, Addison Wesley, 1997
FPGA Components
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FPGAs have several basic components:
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Regular array of basic (programmable) logic cells
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Programmable interconnect for connecting the basic cells into
different configurations
Programming technology for configuring the cells and
programmable interconnect
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Level of complexity and number of different types of logic cells
differs across manufactures and even across families from the
same manufacturer
One-time-programmable (OTP)
Erasable
Programmed on power-up
Custom software used by the designer to create the
configuration file
EGRE 427 Advanced Digital Design
Figures from Application-Specific Integrated Circuits, Michael John Sebastian
Smith, Addison Wesley, 1997
Programming Technology - the Antifuse
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An antifuse is normally open
A high programming voltage is placed across it
This forces a programming current (about 5 mA) through it which
melts the thin insulating dielectric forming a permanent, resistive
silicon link
Figure 4.1 An Actel antifuse. (a) A cross section. (b) A simplified drawing. (c) From above, an antifuse is
approximately the same size as a contact.
EGRE 427 Advanced Digital Design
Figures from Application-Specific Integrated Circuits, Michael John Sebastian
Smith, Addison Wesley, 1997
Actel Antifuses
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Actel antifuse technology uses three additional masks over a
traditional CMOS process
Programming an ACTEL device requires about 5 to 10 minutes per
device
Production programming of more than 1000 or 2000 devices per
week requires a gang (multiple device) programmer
Table 4.1 Number of antifuses
on Actel FPGAs
Device
A1010
A1020
A1225
A1240
A1280
Antifuses
112,000
186,000
250,000
400,000
750,000
antifuse resistance/W
Figure 4.2 Distribution of resistances for blown Actel antifuses.
EGRE 427 Advanced Digital Design
Figures from Application-Specific Integrated Circuits, Michael John Sebastian
Smith, Addison Wesley, 1997
Quicklogic Metal-Metal Antifuse
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Metal-metal antifuses
directly connect metal
wiring layers - thus
eliminating the parasitics
of a polysilicon layer in
between
Direct connections to the
metal layers make it
easier to use larger
programming currents
producing a lower
antifuse resistance
Figure 4.3 Metal-metal antifuse. (a) An idealized cross section. (b) A
metal-metal antifuse in a three-level metal process.
EGRE 427 Advanced Digital Design
Figures from Application-Specific Integrated Circuits, Michael John Sebastian
Smith, Addison Wesley, 1997
Quicklogic Metal-Metal Antifuse
Resistance
Figure 4.4 Distribution of resistance values for the QuickLogic metal-metal antifuse.
EGRE 427 Advanced Digital Design
Figures from Application-Specific Integrated Circuits, Michael John Sebastian
Smith, Addison Wesley, 1997
Configuration via Static RAM
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Configuration data is loaded into static RAM on chip
Static RAM cells control pass transistors which configure the logic
cells and interconnect
FPGA can easily be reconfigured, even on the fly
Power must be maintained to the chip to retain the configuration or
the configuration can be loaded from a PROM on power-up (usually
serially)
Figure 4.5 The Xilinx SRAM configuration cell.
EGRE 427 Advanced Digital Design
Figures from Application-Specific Integrated Circuits, Michael John Sebastian
Smith, Addison Wesley, 1997
EPROM Cell
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Used in EPLD devices and configuration EPROMS
Figure 4.6 An EPROM transistor. (a) With a high programming voltage (> 12V) applied to the
drain, electrons gain enough energy to “jump” onto the floating gate. (b) Electrons
stuck on gate 1 raise the threshold voltage so that the transistor is always off for
normal operating conditions. (c) UV light provides enough energy to the stuck
electrons on gate 1 for them to “jump” back to the bulk.
EGRE 427 Advanced Digital Design
Figures from Application-Specific Integrated Circuits, Michael John Sebastian
Smith, Addison Wesley, 1997
Using FPGAs
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Changing demands from large FPGA users can often result in
supply problems
This is less of a problem in MGA or CBIC ASICs as this is
arranged directly between the customer and foundry although a shortage in ASIC foundry capacity is predicted in
the future
Most FPGAs are intended for direct placement into a PCB
and are thus surface mount devices
Unlike standard PLD devices (e.g. 22V10), FPGA signal and
power pinouts vary widely among vendors
Replacing an FPGA with an MGA or CBIC can be difficult
because of this and may require pin or I/O locking
EGRE 427 Advanced Digital Design
Figures from Application-Specific Integrated Circuits, Michael John Sebastian
Smith, Addison Wesley, 1997
Using FPGAs (cont.)
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Equivalent FPGAs available from different vendors or even
from a single vendor may run faster than expected which can
cause a problem for asynchronous designs
For a given design, there can be a large performance
difference between different FPGA architectures resulting
from differences in the type and mix of logic
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Designers should be careful in choosing a given FPGA to
implement their design
Each type of FPGA (e.g. Actel 1020A) is available in a variety
of configurations for packaging, grade (commercial or
military), speed, and quantity
Pricing is calculated using a base device price and a series of
adjustment factors
EGRE 427 Advanced Digital Design
Figures from Application-Specific Integrated Circuits, Michael John Sebastian
Smith, Addison Wesley, 1997
Actel FPGA Pricing Example
Factor
Base Price
Quantity
Time
Qualification Type
Speed
Package
Estimated Price
Actual Price
EGRE 427 Advanced Digital Design
Example
A1020A
100-999
1H92
Commercial
2
PQ100
Value
$43.30
84%
100%
120%
140%
125%
$76.38
$75.60
Figures from Application-Specific Integrated Circuits, Michael John Sebastian
Smith, Addison Wesley, 1997