Transcript Co-processors for speeding up drug design algoithms

Co-processors for speeding
up drug design algorithms
Advait Jain
Priyanka Jindal
Pulkit Gambhir
Under the guidance of:
Prof. M Balakrishnan
Prof. Kolin Paul
Objective
To design FPGA based hardware
accelerators for speeding up the energy
minimization process.
Single Point Precision
minEnergyCG()
Precision lost
here
diffEnergy()
Instability
introduced here
Resulting in NaN
evalEnergy_for_step()
moveStep()
Single Point Precision

Removed the instability

Parabolic interpolation replaced by lnsearch()
whenever points are colinear.
Time taken to evaluate the energy
increased.
 Increase in the number of calls to
evalEnergy_for_step().

Slow Float Vs Double: Time Plot
Slow Float Vs Double:
# of evalEnergy_for_step() calls
Control Flow
Single Point Precision
(Molecule Size: 2008 SD:100 CG: 150)
# of Calls to:
EvalEnergyforStep()
Double
642
Slow Float
893
From: minEnergyCG() 450
450
From: lnSearch()
192
443
Double
Slow Float
# of Calls to:
lnSearch()
100
177
evalEnergyForStep()
per lnSearch()
1.92
2.5
Reducing the number of Calls

minEnergyCG:
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
Lnsearch :
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Parabolic interpolation – which 3pts to choose.
Iteratively calculates the step size.
When to stop the iteration determined by 2
tolerances.
What we did:

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Pts for parabolic interpolation are further apart
Increased the tolerances till the time to
minimize the energy was same as double.
Then profiled to check the actual energy.
Fast Float Vs Double: Time Plot
Fast Float Vs Double:
# evalEnergy_for_step() calls
Fast Float Vs Double: Energy Plot
Fast Float Vs Double: Energy Plot
Fast Float Vs Double: Energy Plot
Fast Float Vs Double: Energy Plot
Conclusion from this exercise
Located the source of instability.
 However converting to float increased the
time required for the code to run.
 Increasing tolerances again made the
code fast.
 The energy in case of float did not agree
well with double computation.

ADM-XRC-II board
Ongoing Work
Familiarizing ourselves with the ADM-XRCII board.
 Trying to understand sample code for
writing to ZBT RAMs, exchanging data
with the PC.
 Overall block diagram and connections –
understood.
 Timing – need to look at in more depth.

Tentative Schedule

Software Profiling
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Control Flow Analysis
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Flow Diagram
Data parallelism
August - September
Floating point precision requirement
Exploring H/W Options
Early October
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
No. of calls
Cache misses
Effect of parameters
August
Platform Selection
S/W H/W Partitioning
Implementation
Analysis
Mid-October onwards