Transcript CHAPTER 6 Field Effect Transistors (FETs)

Acknowledged to:
Shahrul Ashikin Azmi (PPKSE)
Objectives
 Explain the operation and characteristics of junction
field effect transistors (JFET).
 Understand JFET parameters
 Discuss and analyze how JFETs are biased
 Explain the operation and characteristics of
metal oxide semiconductor field effect transistors
(MOSFET)
 Discuss and analyze how MOSFET are biased
 Troubleshoot FET circuits.
Introduction
• FET – a three-terminal voltage-controlled
device used in amplification and switching
application.
• Field effect transistors controls current by
voltage applied to the gate. The FET’s major
advantage over the BJT is high input resistance.
• 2 basic type of FET: JFET and MOSFET
JFET
The junction field effect transistor, like a BJT, controls current
flow. The difference is the way this is accomplished. The
JFET uses voltage to control the current flow. As you
will recall the transistor uses current flow through the baseemitter junction to control current. JFETs can be used as an
amplifier just like the BJT.
VGG voltage levels control current flow in theVDD, RD circuit.
JFET
• The terminals of a JFET are the source, gate, and
drain.
• A JFET can be either p channel or n channel.
JFET
• VDD provide a drain-to-source voltage.
• VGG sets the reverse-bias voltage between gate and source.
JFET is always operated with gate-source pn junction reversebiased. Reverse-biasing of the gate-source junction with a –ve
gate voltage produces a depletion region along pn junction.
JFET Biasing
 Gate-to-source junction of JFET always reverse-
biased under normal condition.
 Gate-to-source junction never allowed to become
forward-biased because the gate material is not
designed to handle any significant amount of current
 may destroy the component.
 The fact gate is always reverse-biased leads to
important feature  JFET has high gate input
impedance; typically in high megaohm range.
 This feature result to JFET extensively being used in
integrated circuits. Low current draw helps IC remain
cool, thus allowing more components to be placed in
a smaller physical area.
 The JFET is always operated with the gate-source
pn junction reverse-biased.
 Reverse biasing of the gate-source junction with a
negative gate voltage produces a depletion region
along the pn junction, which extends into the n
channel
 thus increases its resistance by restricting the channel
width.
 The channel width and the channel resistance can be
controlled by varying the gate voltage, thereby
controlling the amount of drain current, ID.
JFET Characteristics and Parameters
Let’s first take a look at the effects with a VGS of 0V. This is
produced by shorting the gate to source junction.
JFET Drain Curve
 Refer to JFET drain curve
from point A to B, ID
increases proportionally
with increases of VDD (VDS
increases as VDD
increases).
 In this area, the channel
resistance is essentially
constant because the
depletion region is not large
enough to have significant
effect. [V=IR]
 This is called the ohmic
region (point A to B)
because VDS and ID are
related by Ohm’s Law.
• At point B, the curve levels off and
ID becomes constant.
• The point when ID ceases to
increase regardless of VDD increases
is called the pinch-off voltage, VP
(point B).
• This current is called maximum
drain current (IDSS) and always
specified for the condition, VGS=0V.
This area is called constant-current
area.
• Breakdown (point C) occur when ID
begins to increase rapidly with any
increase in VDS. This of course
undesirable, so JFETs operation is
always well below this value.
Illustration of JFET Drain Curve
JFET Characteristics and Parameters
From this set of curves you can see with increased voltage
applied to the gate, ID decrease and JFET reaches pinch-off at
values of VDS less than VP.
JFET Characteristics and Parameters
JFET Characteristics and Parameters
JFET Characteristics and Parameters
• We know that as VGS is increased ID will decrease. The point
that ID ceases decrease is called cutoff. The amount of VGS
required to do this is called the cutoff voltage (VGS(off ) ).
• The more negative VGS, the smaller ID becomes. When VGS
has sufficiently large negative value, ID is reduced to zero.
It is interesting to note that
pinch-off voltage (Vp) and cutoff
voltage (VGS(off)) are both the
same value only opposite
polarity.
JFET Transfer Characteristic
 For n-channel JFET, VGS(off) is





negative and for p-channel, VGS(off)
is positive.
Bottom end of the curve is at a
point on VGS axis equal to VGS(off)
and the top end of the curve is at a
point on ID axis equal to IDSS
(shorted-gate drain current rating
of the device).
The operating limits of JFET are:
ID=0 when VGS=VGS(off)
ID=IDSS
when VGS = 0
Transfer characteristic curve can be
developed from drain characteristic
curves by plotting values of ID for
the values of VGS taken from the
family of drain curves at pinch-off.
Show example 8-1 (pg391)
JFET Characteristics and Parameters
The transfer characteristic curve illustrates the control VGS has on
ID from cutoff (VGS(off) ) to pinchoff (VP). Note the parabolic shape.
The formula below can be used to determine drain current. All
these values are usually available from data sheet.
ID = IDSS(1 - VGS/VGS(off))2
JFET Forward Transfer Conductance
Forward transfer
conductance, gm of JFETs
is the changes in ID based
on changes in VGS with VDS
is constant.
Forward transfer
conductance referred to as
gm = ∆ID /∆VGS.
Unit is Siemens (s)
The value is larger at the top
of the curve (near VGS=0) but
become smaller as you
increase VGS (near VGS(off)).
Transconductance
At VGS =0, the parameter is
known as minimum transfer
conductance, gmo and can
be calculated using this
equation:
gmo = 2IDSS/|VGS(off)| and
gm = gmo(1 - VGS/VGS(off))
gmo can be read from the
datasheet as gfs or yfs and
sometimes written as
Forward Transfer
Admittance.
Example
JFET Input Resistance
Since JFET is reverse-biased for operation, its input
resistance becomes so large. This is an advantage of using
JFET. Looking at the datasheet, you may calculate the
resistance value by using the Gate Reverse Current IGSS.
This internal input resistance can be calculated at different
VGS :
RIN=|VGS/IGSS|
As IGSS increases with temperature, RIN will decrease.
JFET Input Resistance
Example 1:
Calculate RIN if IGSS=-2nA and VGS=-20V
Solution:
RIN=|VGS/IGSS|=|-20/-2n|=10G
JFET Biasing Circuit
• Just as we learned that the bi-polar junction transistor
must be biased for proper operation, the JFET also must be
biased for operation.
•Let’s look at some of the methods for biasing JFETs.
•In most cases the ideal Q-point will be the middle of the
transfer characteristic curve which is about half of the IDSS.
•4 types of bias method are self-bias, gate-bias, voltagedivider bias and current-source bias.
JFET Biasing- Self bias
• Self-bias is the most
common type of biasing
method for JFETs.
•Notice there is no voltage
applied to the gate, VG=0V.
•However, the voltage from
gate to source (VGS) will be
negative for n channel and
positive for p channel to keep
the junction reverse biased.
JFET Biasing- Self bias
• Uses a source resistor to help
reverse bias JFET gate. The gate
is returned to ground via RG, and
RS has been added to source
circuit.
• This voltage can be determined
using the formulas below.
•ID = IS for all JFET circuits.
VG=0 and VS=IDRS.
VGS = VG - VS
(n channel) VGS = 0-IDRS
=-IDRS
(p channel) VGS = 0-(-IDRS )
=IDRS
JFET Biasing – self bias
 Keep in mind that analysis
of p-channel is the same as
n-channel except for
opposite polarity voltages.
 The drain voltage with
respect to ground is:
VD = VDD – IDRD
 Since VS = IDRS, VDS is:
VDS = VD – VS
= VDD – ID(RD+RS)
JFET Biasing-self bias
• Setting the Q-point requires us to determine
a value of RS that will give us the desired ID
and VGS. The formula below shows the
relationship.
RS = | VGS/ID |
• For a desired value of VGS, ID can be
determined from the either the transfer
characteristic curve or more practically from
the formula below. The data sheet provides
the IDSS and VGS(off).
ID = IDSS(1 - VGS/VGS(off))2
JFET Midpoint Biasing-self bias-formula
method
Midpoint biasing- desirable to bias a JFET near the
midpoint of its transfer characteristic curve where ID =IDSS /
2. ID is approximately one-half of IDSS when:
VGS  VGS(off)/3.4
2
2




V
/
3
.
4
V
GS
(
off
)
  0.5I DSS
I D  I DSS 1  GS   I DSS 1 
 V



V
GS ( off ) 
GS ( off )



JFET Midpoint Biasing-self bias-formula
method
The value of RS needed to establish VGS can be determined
by the relationship below.
RS = | VGS/ID |
To set the drain voltage at midpoint (VD=VDD/2), select a
value of RD to produce the desired voltage drop.
The value of RD needed can be determined by taking half of
VDD and dividing it by ID.
RD = (VDD/2)/ID
JFET Biasing- self-bias
Remember the purpose of biasing is
to set a dc operating point (Q-point).
In a self-biasing type JFET circuit, the
Q-point is determined by the given
parameters of the JFET itself and
values of RS and RD. Setting it at
midpoint on the drain curve is most
common.
One thing not mentioned in the
discussion is RG. It’s value is arbitrary
large to prevent loading on the driving
stage in a cascaded amplifier
arrangement.
JFET Midpoint Biasing-self bias-graphical
method
The transfer characteristic curve along with other parameters
can be used to determine the mid-point bias Q-point of a selfbiased JFET circuit.
First, establish dc load line by calculating VGS.
VGS = -IDRS for ID=0 and ID=IDSS
With 2 points (ID=0 and ID=IDSS), draw dc load line on the
transfer characteristic curve.
The point where the two lines intersect gives us the ID and VGS
(Q-point) needed for mid-point bias. Note that load line
extends from VGS(off)(ID= 0A) to VP(ID = IDSS)
JFET Midpoint Biasing-self bias-graphical
method
JFET Biasing- voltage divider bias-formula
• Voltage-divider bias can also be used
to bias a JFET. R1 and R2 are used to keep
the gate-source junction in reverse bias.
Operation is no different from self-bias.
Determining VGS for a JFET voltage-divider
circuit with givenVD can be calculated with
the formulas below.
Source voltage,VS = IDRS
Gate voltage, VG =(R2/R1+R2)VDD
Gate-to-source voltage.VGS=VG –VS
Source voltage, VS = VG - VGS
JFET Biasing- voltage-divider bias formula
 VS must be more +ve than VG in order to keep VGS reverse-biased (-ve value).
Drain current, ID = (VDD – VD)/RD or
Since ID=IS, then ID=VS/RS
JFET Biasing-voltage-divider biasgraphical
• In using the transfer characteristic curve to determine the
approximate Q-point we must establish the 2 points for the
load line.
•1st step draw dc load line:
• The first point is ID = 0 and VGS =VG.
VS=IDRS=(0)RS=0V
VGS=VG-VS=VG-0=VG
 The 2nd point is for VGS=0,
ID=(VG-VGS) / RS = VG / RS
ID=VG / RS and VGS=0.
• The point at which the load line intersect with transfer characteristic
curve is Q-point.
Dc load line for JFET with voltage-divider bias
JFET Biasing – Current Source Bias
 Current source bias  provides
high Q-point stability by making
value of ID independently of JFET.
 From figure, JFET drain current
equals BJT collector current. IDQ
= IC
 In this circuit, a BJT acts as the
constant-current source because its
emitter current is essentially
constant if
 A FET can also be used as a constant
current source.
JFET Biasing- Current source bias
 Advantage: provide the most
stable Q-point value of ID.
 Disadvantage: circuit
complexity makes it undesirable
for most applications.
JFET Biasing
Transfer characteristics can vary for JFETs of the
same type. This would adversely affect the Qpoint for self-bias analysis. Q-point is much more
stable using voltage-divider bias and current
source bias.