Transcript Gradient.PPS

A Temperature-Aware Design Methodology
for
Die-Level Thermal Analysis
Nanda Gopal
Gradient Design Automation
MEPTEC 2006
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Outline
 Introduction
 Thermal Effects on Circuit Performance
 FireBolt™ Thermal Analysis Engine
 Temperature-Aware Design Methodology
 Bridging the Thermal Modeling Gap
 Conclusion
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The Thermal Modeling Gap
 Chip assembly is too often a one-way process
 Thermal models of the die and package are developed
with scarce knowledge of each other
 There is a clear gap in the thermal modeling flow
 The increasing dominance of temperature as a
performance limiting factor requires this gap be bridged
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Technology Impacts on Chip Behavior
 Process trends:
Lower device thresholds
 Increased leakage current
Finer geometries
 Higher wire resistance
Copper metallization
 Higher conductor currents
Low-k dielectrics
 Poor thermal conductivity
 Design trends:
Larger die size
 Increased device count
Increasing complexity
 Mixed-signal, multi-core, SIP, …
Increasing performance
 Increased total power
Aggressive power managemnt
 Highly variant chip power profile
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Die Temperature is Not Uniform/Constant
 On-chip temperature can vary by as much as 500C
 Spatial temperature distribution will never attain a uniform,
Temperature
constant value as long as the power distribution varies
y
x
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Design Challenges at Nanometer Processes
Power
Voltage Drop
90nm
65nm
Temperature
Electromigration
Signal Integrity
130nm
Timing Closure
180nm
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Thermal Impact on Power
 Leakage power is seen as dominant at 90nm and below
 Device leakage is exponentially dependent on temperature
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Thermal Effects on Timing
 Cell performance is impacted by voltage drop & temperature
 Clock skews are extremely sensitive to on-chip variations
 “Delay inversion” effects are being observed at 65nm
5% change in Vdd
increases cell delay by
>11%
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Thermal Impact on Reliability
 Black’s equation is used to calculate Mean Time To Failure
(
MTTF = A .
Jav-n .
e
k.(Tref
Q
)
+ T(Jrms))
Self heating not
considered today
 Exponential dependence of MTTF on temperature can
drastically reduce product lifetimes
 50-75 years @ 60oC  1000-1500 hrs @ 90oC
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Current Design Methodology
 Lack of predictive and
Location of thermal
diode
deterministic
temperature
data
 Analysis tools run with inaccurate thermal assumptions
Temperature incorrectly deduced from power
 Undetected potential failures
 Costly guard-bands and over-design
 Poor product reliability
 Thermal management systems inadequate
 IncorrectPeak
placement of temperature sensing diodes
temperature
 Self-heat in metallization ignored
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FireBolt Thermal Analysis Engine
Design
layout
Power
profile
Thermal
layers
Package
model
Temperature vs
leakage power
table
Begin thermal analysis
Annotate initial source power
Construct 3D thermal model
Update power(T)
Solve for 3D temperature
End
EM analysis
Cell
temps
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Wire
temps
Final
powers
Timing analysis
IR drop analysis
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FireBolt Technology
 Innovative, high capacity, adaptive algorithms
 Incorporation of package and boundary conditions
 Bond wire/bumps, molding compounds, epoxies, etc.
 True 3D modeling and analysis
 Power sources on all layers (devices, wires, vias)
 Mixed-level analysis (block  device)
 Detailed temperature for all design objects on all layers
 Comprehensive data visualization
 Temperature, power, power density, heat flux, …
 Built on the OpenAccess data model for easy integration
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FireBolt Data Visualization
Temperature
Power
Thermal
3D
Isotherms
Thermal
Contours
Surface
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Silicon Verification
Test Case
Power
(W)
θJA
(K/W)
Tj (°C)
FireBolt (°C)
measured
using on-chip
diode
thermal
analysis result
Epad1
2.19
29.7
87
87.91
Epad2
2.18
29.4
86
86.97
Slug1
2.13
28.2
82
82.96
Slug2
2.12
27.8
81
81.88
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Thermally-Aware Design Flow
Performance-driven Design Flow
LEF
DEF
SDC
Package
lib
Build physical prototype
layout
Run power analysis
power
FireBolt
3D thermal analysis
Thermal delay calculator
Run rail analysis
Run timing analysis
Layers
SPEF
Incr. SDF
Thermal repair
Run final optimizations
Run final route
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Package Models
 Package models have viewed the die as a point heat source
while increasing the resolution of the package itself
 Distributed die temperature must now be considered in the
package world to improve overall accuracy
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Bridging the Thermal Model Gap
 Accuracy of package thermal prediction can be improved by
coupling 3D package simulation with FireBolt
 Allows inclusion of complex cooling mechanisms
 Provides a bridge between package and design worlds
Packaging
Flomerics
FireBolt
Package model
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Design
Die thermal profile
Design
Layout
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Iterative Refinement of Thermal Models
Package model at horizontal face of die
FireBolt
Flomerics
Thermal profile at horizontal face of die
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Effect of Die Temperature on Air Flow
Air flow
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Conclusion
 Chip-level thermal analysis is essential for designs <90nm
 Thermal analysis must include the effects of the package
 On-chip temperature variation affects circuit and package design
 FireBolt is the first commercial EDA tool to combine data from
process/package/circuit design to compute 3D chip temperature
 Tool architecture and interface modules allow for seamless
interaction with other tools and capabilities
 Current EDA tools and flows must incorporate thermal information
as early as possible to avoid temperature-induced design issues
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