ppt - EC - Unit 1 - Transistor, UJT, SCR

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Transcript ppt - EC - Unit 1 - Transistor, UJT, SCR

Unit 1
Transistors, UJTs and
Thyristors
Unit 1: Transistors, UJTs and
Thyristors
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Objectives:
Operating Point
CE configuration
Thermal runaway
UJT
SCR
1.1 Operating (Q) Point
To design an amplifier:
1. DC & AC analysis
2. Operating Point in active region
 by biasing circuits
1.
2.
3.
4.
Fixed bias
Emitter bias
Collector-to-base bias
Voltage divider bias with emitter bias
…selecting suitable Q point
…selecting suitable Q point
• Point A no bias
Cut-off region
• Point B near to knee portion
 Do not allow more output swing
• Point C close to PD(max) curve
 Output’s +ve swing is limited
• Point D middle of active region
Allows +ve & -ve excursions of output
1.2 CE configuration
•
Popular as provides considerable AV & AI
To learn:
• Biasing Circuits:
1. Fixed bias
2. Emitter bias (self bias)
3. Voltage divider bias with emitter bias
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Analysis: DC, load-line
•
merits & demerits
fixed bias circuit
• Simplest
• Biasing components:
– 2 resistors (RB & RC)
– Vcc
• BE junction FB by Vcc through RB (100s of kΩ)
• CB junction RB by Vcc through Rc (few k Ω)
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DC analysis
To get DC
equivalent
circuit:
Open Circuit
all capacitors,
and
redraw the circuit
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…
From fundamentals
• VBE = VB – VE
Similarly
• VCE = VC – VE
Next, by KVL to BE loop
VCC – IBRB – VBE = 0
VCC – VBE
 IB = ----------------RB
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…
But IC = β IB
where β is transistor gain
VCC - VBE
IC = β ( ---------------- )
RB
VCC
IC = β ( ---------- )
RB
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Unit 1: Transistors, UJTs and SCR
-----(1)
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…
β VCC
IC ≈ -----------RB
IC
Where β is transistor current gain = -----IB
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…
Next, apply KVL to
output loop,
VCC = ICRC + VCE
VCE = VCC – ICRC
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----(2)
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Put Ic = 0 in eqn (2)
∴ VCE = Vcc
Put VCE = 0 in eqn (2)
∴ Ic = Vcc / Ic
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…
• Q point is influenced by
– IB – base current
– RC – collector resistance
– VCC – supply voltage
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Numerical example:
Find values of
ICQ & VCQ
Find values of
IC & VCE,
forcing each
value to zero,
each time
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Solution:
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• Thus,
ICQ = 1.43 mA & VCEQ = 9.28 V
Which are the coordinates of Q point
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Emitter bias / self bias configuration
• Additional resistor RE, improves stability,
as it produces negative feedback.
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DC analysis
• By KVL to input base loop,
VCC – IB RB – VBE – IE RE= 0
VCC – VBE
IB = -------------------- ----(1)
RB + (β+1)RE
…
neglecting VBE
VCC
IB = -------------------RB + (β+1)RE
Compare this equation with
Iin =
Vin
-------Rin
From basics,
IC = IB + IE
IB is <<
…
 IE = IC
We get input resistance = RB + (β+1)RE
Next, applying KVL to output collector loop,
VCC – IC RC – VCE – IE RE = 0
VCE = VCC – IC (RC + RE)
------(2)
…
Also VE = IE RE = IC RE
From eqn. (1) & (2)
VCC – VBE
ICQ = β -------------------RB + (β+1)RE
VCEQ = VCC – IC (RC + RE)
The coordinates
of Q point
Load line analysis
We have
VCE = VCC – IC (RC + RE)
Put IC = 0
VCE = VCC│IC = 0 is point of load line on
x – axis (VCC, 0)
…
For second point,
Put VCE = 0
VCC
IC = --------------(RC + RE)
VCE = 0
…
thus we have
on y- axis
(0, VCC/(RC + RE))
as another
point on load line.
How stability increased:
ICQ
VCC – VBE
= β -------------------RB + (β+1)RE
VCEQ = VCC – IC (RC + RE)
RE introduces negative (ac emitter) feedback, due to which
•
Stability of Av increases
How stability is improved by RE:
IE ≈ Ic
IE = VE / RE
IE
VE
Due to temperature or else, IC
VCC = IB RB + VBE + VE
IC
Initial increase
and later
decrease
proves that RE
improves
stability
IB = β IB
VBE
IB
VBE = IB RB
AC and DC Currents in an Amplifier:
Small Signal
Operation:
ICQ
IC = ICQ + ic
ic
IBQ
ib
IE = IEQ + ie
IB = IBQ + ib
IEQ
ie
Numerical example:
• Refer to figure. Find the values of RB, RC &
RB, given that IB=40µA, VE=2V, IC=4mA,
VCE=12V & supply voltage VCC=15V. Assume
silicon transistor.
Numerical:
Numerical:
3. Voltage-divider-bias with emitter-bias configuration:
• Stability further
improved, ( but gain
decreases)
• Most commonly used
configuration
• Gain can be improved
by bypass capacitor,
later studied.
DC equivalent circuit:
To get DC equivalent
circuit:
Open Circuit all capacitors,
and
redraw the circuit
DC analysis
2 methods:
1. Accurate method (uses Thevenin’s theorem)
2. Approximate method
1. Accurate Method:
Using Thevenin’s Theorem:
DC Equivalent Circuit
Redrawn showing Vcc
Thevenin’s Equivalent
Circuit
Calculating RTH & VTH:
RTH:
Identify the 2 points
short circuit all
DC voltages
Little
consideration will
show that –
RTH is = parallel
combination of
RB1 & RB2
RTH = RB1 ║ RB2
RTH
VTH:
Consider the circuit, again –
VTH is nothing but – the voltage across the 2
points OR across RB2
VTH
RB2 VCC
VTH = ---------------(RB1 + RB2)
Now replace the base circuit with Thevenin’s
equivalent
circuit
IE
IC + IB
IE = IC + IB
Dividing by IC, as it is to be eliminated,
---- = ----IC
IC
----IC
1
= 1 + ---β
β + 1
= ---------β
IC (β + 1)
= -------------IC / IB
IE
= IB (β + 1)
• Applying KVL to the
base loop –
VTH – IB RTH – VBE – IE RE = 0
Substituting IE = (β+1)IB
VTH - VBE
IB = ---------------------RTH + (β+1)RE
…
VTH - VBE
IBQ = β --------------------RTH + (β+1)RE
-----(1)
By KVL to output collector loop,
VCC –IC RC – VCE – IE VE = 0
VCE = VCC – IC RC – IC RE
VCEQ = VCC – ICQ (RC + RE)
as IC = IE
-----(2)
Hence equations (1) & (2) represent Q point.
Load line analysis:
• Same as that of emitter bias:
Advantages & disadvantages of VDB:
• Excellent stability (against temperature & β),
because of –ve feedback introduced by RE.
• But RE reduces gain AV.
• Again CE bypasses ac signal, increasing AV,
also maintaining stability.
DC do not pass through CE as
f=0 in XC = 1 / (2πfC)= resistance
IE
ie
Numerical:
Solution:
4. Collector-to-base bias configuration:
Little bit looking back:
We have studied –
1. base bias
2. emitter (self) bias
3. voltage-divider-bias with emitter-bias
with,
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DC analysis (to know Q point/ICQ & VCEQ)
•
load-line analysis (points A & B of loadline)
• RB provides negative feedback, voltage-shunt
feedback
• Better (not excellent, as VDB with EB)
stability
DC analysis:
IB + IC
IB
IC
• KVL to base-emitter loop,
VCC – (IB + IC) RC – IB RB – VBE = 0
• Substitute IC = β IB
VCC – VBE
IB = --------------------RB + (β + 1) RC
VCC – VBE
ICQ = β --------------------RB + (β + 1) RC
-----(1)
• KVL to collector-emitter loop,
VCC – (IB + IC) RC –VCE = 0
VCE = VCC – (IB + IC) RC
• Ignoring IB,
VCE = VCC – IC RC
At quiescent conditions,
VCEQ = VCC – ICQ RC
-----(2)
Advantages & disadvantages:
• Provides stability
• Reduced gain, due to –ve feedback, can be
reduced by bypassing capacitor, as shown
below,
We are not studying …
•
•
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4.3 Common base circuit
4.4 Common collector circuit
4.5 Bias stabilization
4.6 Bias compensation
But let us now study …
• 4.7 Thermal Runaway
4.7 Thermal Runaway
• Power dissipation depends on
• Physical size
• Its construction
• Mounting arrangement
• Maximum power rating is limited by
• Temperature that CB junction can withstand
• Ambient temperature
• When ambient temperature , power rating ,
is known as “power derating”
…
• Power dissipation capability range – 100s
milliwatts to 250 Watts
• Max. CB temperature – Si – 150 °C to 225 °C
– Ge – 60 °C to 100 °C
Power
dissipation
PD
PD(MAX)
100
Typical power derating curve
Maximum operating
temperature
200
Case
temperature
°C
Defn.:
when the transistor is in operation it
dissipates power & its junction temperature
rises, which in turn causes collector current to
increase. This may lead to more power
dissipation & further increase in temperature &
subsequent increase in collector current. If this
cycle continues, it may result in permanent
damage to the transistor. This phenomenon is
known as “Thermal Runaway”.
PD  Tj  IC
…
• Steady state junction temperature,
Tj – TA = θ PD
Where
Tj – junction temperature
TA – ambient temperature
PD – power dissipated in transistor
θ – thermal resistance °C/W
Thermal Resistance:
ratio of the rise in transistor junction
temperature to the amount of power dissipated.
Which depends on –
• Transistor size
• Size of heat sink
• Other cooling method, such as forced air
Thermal resistance (θ):
Tj – TA
dTj
θ = ----------- = -------PD
dPD
dPD
1
----------- = -------dTj
θ
Operating Point considerations against thermal
run-away:
At Q2:
IC ↑  Q2 to move on
100mW curve  PD ↓ 
thermally stable
At Q3:
IC ↑  Q3 to move on
200mW curve  PD ↑ 
thermally instable 
checked for thermal
runaway
4.8 Transistor switch
• Another major application of transistor is
Switch
…
While designing,
Transistor is heavily saturated
IC(sat) = VCC / RC
IB(sat) = IC(sat)/ β
Usually IB(max) = IB(sat) x 0.25
The minimum i/p voltage to drive
transistor in saturation is
VIH = IB(max) RB + VBE
Rsat = VCE(sat) / IC(sat) ≈ few tens of
Ohms
Transistor Switching Delay:
During ON:
tD=delay time=to 10%
tr=rise time=10% to
90%
turn-ON time=tD+tr
During OFF:
ts=storage time=fall to
10%
tf=fall time=90% to
10%
toff=turn-OFF time
=ts+tf
Numerical:
An input pulse is applied to the transistor
switch shown in figure. What is the
minimum input voltage required to make
the LED glow? It is given that the
minimum current required by the LED to
glow is 10mA, voltage drop across LED
is 1.5V, BE voltage 0.7V, CE voltage at
saturation is 0.5V.
2..IC(sat) ?
VCE(sat) = 0.5V
1..Vp ?
IB=IC / β
=10mA / 100 VBE = 0.7V
= 1µA
IE=IC=
10mA
3..IB(sat) ?
4..IB(max) ?
=β x IC(sat)
=1.25 x IB(sat)
1.5V
UJT (unijunction transistor)
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•
Only 1 pn junction, unlike 2 (BE & CB)
Current controlled
Negative resistance exists
May be used as switch
Construction:
Equivalent Circuit:
Intrinsic stand-off ratio:
 = RBB1 / (RBB1 + RBB2)
VI characteristics:
VP = VBB + V
Operation:
when VE ↑  -IEO reaches 0, then ↑ to IP at VP, IE ↑
with VE ↓ up to IV & VV known as negative
resistance, further behaves as a normal resistance.
UJT Relaxation Oscillator:
SCR (silicon controlled rectifier):
Operation:
A momentary pulse
applied to the gate
increases the base
current of npn
transistor initiating
regenerative
feedback action;.
This action
ultimately drives
both transistors to
saturation causing
switching-ON by
conducting heavily.
Characteristics:
BEFB
CB
CB
BE  FB
Questions:
1. Explain selecting a suitable operating point
(104)
2. Explain DC & load-line analysis of fixed
bias (105)
3. What are the parameters that vary the Q –
point (ans:- IB, RC, VCC -108)
4. Problem 4.1 (109)
5. Explain DC & load-line analysis of emitter /
self bias (110)
6. Problem 4.2 & 4.3 (113)
7. Explain DC & load-line analysis of VDB with EB
circuit (115)
8. Problem 4.4 (119)
9. Explain DC & load-line analysis of collector-tobase bias (124)
10. Problem 4.7 (127)
11. Define thermal runaway. Explain operating point
considerations in thermal runaway (147)
12. Explain transistor as a switch. Brief about switching
delays (152)
13. Explain UJT, relaxation oscillator (215)
14. Explain SCR (227)
End
of
Unit 1: Transistors, UJT & Thyristors
IC (Integrated Circuit)
Overview
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Vin = HIGH (≈5Volts)
Saturation region,
IC(sat)=VCC / RC
VCE = VCC - IC(sat) RC
= 0 Volt
= logic LOW
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Cut-off region,
IC ≈ 0
VCE = VCC - IC RC
= logic LOW
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