Transcript Accumulation Model

Hardware Reliability Margining for the
Dark Silicon Era
Liangzhen Lai and Puneet Gupta
Department of Electrical Engineering
University of California, Los Angeles
[email protected]
This work is supported in part by NSF Variability Expedition grant CCF-1029030
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Outline

Overview

Accumulation Model and Management Policies

Problem Formulation

Experimental Results

Conclusion
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Hardware Reliability Margin
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Parametric margin
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Physical margin
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Voltage/Frequency or sign-off corners
E.g., BTI, HCI
Metal width, layout spacing
E.g., current-dependent minimum metal width for EM
Typically worst-case driven
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Mostly derived at hardware design time
Uncertainty in workload, circuit operating points etc.
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Reliability vs. Operating Points
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Most reliability-related phenomena depends heavily
on the circuit operating points
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Voltage, Frequency, Temperature etc.
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Dynamic Range of Operations
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Efficiency needed for the Dark Silicon Era
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Multi/Many-core design with less powerful cores
Low voltage/current/power -> less margin
“Turbo X”: Turbo Boost (Intel), Turbo Core (AMD)
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Under certain conditions
High voltage/current/power-> more margin
Moderate
Parallel
Known optimistic
Low stress states
Workload
Reliability
margin
High stress states
Intensive
Single-thread
Known pessimistic
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Dark Silicon Contexts
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Pessimism depends on the difference between
peak power/temperature and sustainable
power/temperature
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Power constraint
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Quantify silicon “darkness”
Dark ratio:
Limit on maximum instantaneous power
Thermal constraint
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Limit on maximum on-chip temperature
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Margining Methodology
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Formulate as workload optimization
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Maximize the reliability degradation
Still meets the power/thermal constraints
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Outline

Overview

Accumulation Model and Management Policies

Problem Formulation

Experimental Results

Conclusion
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Dynamic Reliability Model
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Most reliability models are static
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Derived for constant voltage/current/temperature
Need a highly dynamic model for optimization
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Comparing different degradation scenarios
v
v
P1
P3
P1
vs.
P3
t
P2
t
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Accumulation Model
Time spent in
each power
states
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Some can be derived from the model itself
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Accumulation
Model
Worst-case
degradation
at the end of
lifetime
E.g., EM can be modeled by effective current density Jeff
Other can be derived by simulator
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E.g. Worst-case BTI degradation can be derived by
simulating different power state ordering and picking the
worst-case
Fitting and interpolation can also be used
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Spatial problem vs. Temporal problem
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With accumulation model, reliability degradation
can be modeled as temporal distribution problems
v
P1
P2
P3
t

The workload and power/thermal constraints are
spatial problems
P1
P3
P1
P2
P1
P2
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System Management Policy
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We assume a fair round-robin policy
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Iterate scheduling priorities among all processor cores
Iterating frequency can be of hours to days
Assuming this policy because:
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Simple: open-loop, reasonable to assume at hardware
design time
Effective: sufficient iterations to balance workload during
typical hardware life time of multiple years
Pessimistic: more sophisticated policies are likely to
perform better, i.e., margin is pessimistic
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Bridging Spatial and Temporal Problems
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Management policy will iterate workload among all
cores
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Spatial distribution is equivalent to temporal distribution
v
P1
P3
P1
P2
P1
P2
P1
P2
P3
t
Spatial
constraints
Temporal
distribution
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Outline

Overview

Accumulation Model and Management Policies

Problem Formulation

Experimental Results

Conclusion
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Optimization Under Power Constraints
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x is the number of cores at each power states
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Also the input to the accumulation model f(x)
P is the power corresponding to the power states
Pmax is the power constraint
Formulated as Integer Linear Programing (ILP)
problem
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Thermal Problem
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Thermal limit can be reached by two scenarios
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Heat up then cool down (left)
Constant temperature (right)
The constant stress will result in worse degradation
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Higher average temperature
More time in high power state
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Optimization Under Thermal Constraints
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S is time spend in each power states for each cores
A is the temperature sensitivity matrix
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Temperature increase per unit power
Tmax is the maximum temperature constraint
Tbak is the background power for each cores
Formulated as Linear Programming (LP) problem
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Outline

Overview

Accumulation Model and Management Policies

Problem Formulation

Experimental Results

Conclusion
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Experimental Setup
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Power model
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Thermal model
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Based on a commercial processor benchmark
Using libraries characterized at different supply voltages
from 0.6V to 0.9V
Using HotSpot simulator
Consider the cases of 2x2, 4x4, 8x8 and 16x16
cores
BTI: both NBTI and PBTI
EM: metal sized to have the same current density
(MTTF)
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Local Power Network EM Results
Power constraint
40% reduction
Thermal constraint
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Signal Wire EM Results
Power constraint
60% reduction
Thermal constraint
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BTI Results
20%
reduction
Power constraint
Thermal constraint
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Conclusion
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We propose hardware reliability margining
methodology for chips in the dark silicon era
We formulate the margining problem under power
and thermal constraints
Experimental results show that at 60% dark ratio,
our method can achieve 40%-60% reduction in
metal width margin and 20% reduction in BTI delay
margin
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Backup slides
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EM Accumulation Model
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Effective current density:
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For local power mesh
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Jeff can be calculated by average power consumed
For signal wires:
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Jeff is proportional to V * f
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BTI Accumulation Model
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Two steps:
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Identify the worst-case ordering by simulator
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Worst BTI degradation happen when power states are
applied in increasing order of stress voltages
Fitting the accumulation model
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First pick a set of power state distribution sample x
Simulate the degradation g(x)
Assuming the fitting function is
Formulated as:
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