Transcript Project on Web Desig..

Web Design of GMRT Digital
Backend
Anvesh Ghritlahre
STP Student
NITW
G.M.R.T. DIGITAL BACK-END
• Performs the Digital Signal Processing of the
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analog signal from the base-band system
Digitizes the analog signal, calculates the cross
amplitude and phase information for the 30
antenna array
Synthesis the Stokes Parameters which is used
in Pulsar studies
Stores data for further observations
Digital Back-end
Classification of the Digital Back-end
• The Digital Back-end can be broadly divided
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into:
The correlator section is responsible for the
analog to digital conversion ( ADC subsystem),
nullify the delay introduced ( Delay DPC ) and
perform the FFT ( FFT subsystem ) and
multiply and accumulate data ( MAC )
The Pulsar Receiver calculates the Stokes
Parameters needed for Pulsar Research
The Correlator Section
• The correlator section can be divided
into
• Sampler ( ADC Subsystem )
• Delay DPC Subsystem
• FFT Subsystem
• MAC Subsystem
Sampler ( ADC Subsystem )
• It is the front-end of the correlator system
• Converts analog signals from various
antennas into digital format for further
processing
• Takes analog input from the baseband
system
• Gives digital 6-bit signal as the output
ADC CARD
• The active card of the ADC system
• Takes two analog inputs, gives 6-bit digital output
Features of ADC Section
Clock Rate
32 Msamples/Sec.
No. of bits
8-bits (only 6 msb bits used).
Analog Input Voltage
+/-1 Vpp.
Input Power Level
0 dBm.
Output Logic Levels
ECL Level.
ADC chip used
AD9058 – Flash type ADC
Delay DPC Section
• Performs the Noise switching & Walsh demodulation of the signal
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from the ADC Subsection, RFI mitigation in time domain is also
performed
Conversion of unsigned 6 bits from ADC to 4 bits sign magnitude
form is done
Channel multiplexing at the output ( as needed for the full polar
mode ) is also performed
Dual clock support is present to take care of extra overhead cycles
in the FFT
Hardware has been implemented using two Altera FPGA devices per
antenna ( all 4 channels ) on one board, and PLDs for bus
arbitration logics
Delay DPC Card
Top View
Rear View
FFT Subsystem
• Two FFT cards are required to process signals from one
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antenna
Complex numbers to be multiplied and accumulated in
the MAC come from outputs of the FFT cards
In Indian Polar mode as well as Non-Polar mode, FFTs in
one side band system outputs signals from Upper Side
Band and FFTs in other sideband system output signals
from Lower Side Band ( total BW is 32MHz )
In Full polar mode all FFT cards outputs signals from
same sideband ( USB or LSB total BW is 16Mhz )
FFT output is in 12 bit ( 4 bits real, 4 bits imaginary and
4 bits common exponent ) format since FX ASIC in MAC
mode accepts input in this format
FFT Card
• Each FFT card has two pipelines to process Right and Left circular
polarization independently
• FFT card performs N ( 512 ) point FFT on the incoming data and
gives N/2 ( 256 ) channels as output. The output from two pipelines
is multiplexed to maintain the 32Ms/sec data rate which is the
required data rate for the MAC
• ASICs are used as basic building block for FFT operation, each
operates at 32.25 MHz clock speed. This is different from 32 MHz
sampling clock, mainly to accommodate the extra four overhead
clock cycles consumed by FFT operation
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The FFT operation is pipelined and uses Divide and Conquer Approach
algorithm to compute a 512 point FFT. Five ASICs per pipeline are used to
calculate the 512 point FFT operation, with the operations split as radix 2,
4, 4, 4 & 4 computations
The output from the FFT card is always in time multiplexed fashion
( R & L polarization ) but depends on the mode selected at the DPC
subsystem
FFT Card with Pipeline Board
MAC Subsystem
• MAC sub-system Multiplies and Accumulates the signals from each
pair of 30 antennas
• It provides a 30x30 matrix for each of 2 sidebands & 2 polarisations,
with 256 spectral channels per sideband
• MAC sub-system Multiplies and Accumulates the signals from each
pair of 30 antennas. It provides a 30x30 matrix for each of 2
sidebands & 2 polarisations, with 256 spectral channels per
Sideband
• Visibilities are output at the rate of once every 128 ms
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Number of spectral channels is :
128 in 32 MHz BW, Indian Polar,
128 in 16 MHz BW, Full Polar,
256 in 16 MHz BW, Non-polar.
MAC Card
• The most integral part of the MAC Subsystem is the MAC
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card
The MAC card has an ASIC chip which is its fundamental
element. Each ASIC takes input from 2 FFT cards, 12
bits each
The inputs go to registers and they get multiplied and
then accumulated for the N number of FFT cycles. The
accumulated data of one cycle is stored in the first bank
of the ASIC RAM, which is 256 * 36 ( # of spectral
channels * Bits in output 15,15,6 )
In the next cycle, MAC operation uses the second bank
of the ASIC RAM. During the four dead cycles, the Data
goes to the acquisition machine through back plane and
DAS card.
ASIC & MAC Chip Layout
ASIC Chip
MAC Chip
MAC Card
The Pulsar Receiver Section
• The GMRT Pulsar Receiver provides high time
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resolution, “single dish” output by suitably
adding the signals from individual antennas of
the GMRT
The Pulsar Back-end can be subdivided into :
The G.M.R.T. Array Combiner
The Polarimeter
The IA & PA Receiver
Block Diagram of Pulsar
Back-end
Data Flow
Diagram of
Pulsar
Receiver
G.M.R.T. Array Combiner
( GAC )
• GAC is designed to facilitate the single beam made
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observations for G.M.R.T
The GAC hardware is realised using the PROM based
pipe-lined combiner network
The GAC allows any user selected set of antenna signals
to be added to get the array output
Both single beam modes ( IA & PA ) are available
simultaneously to facilitate more than one kind of
observations possible at the same time
GAC Functional Block
Polarimeter
• The Polarimeter has been developed for G.M.R.T. at the
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Raman Research Institute, Bangalore, India
The Polarimeter is designed primarily for use with the
G.M.R.T. radio telescope and perform the above
mentioned operations over dual, orthogonal-polarization
data samples of 512 frequency channels covering a
maximum bandwidth of 32MHz
The digital design exploits the advantages in using lookup tables, reprogrammable logic circuits and DSP chips
to provide full programmability and a modular
architecture so that the bandwidth can be scaled from
1MHz to 32MHz and interfaced to work with any other
telescope
Polarimeter Block Diagram
The IA & PA Receiver
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The two back-ends ( IA & PA ) allow the raw data stream from the
GAC to be integrated in time / frequency to achieve a net data rate
at which the signals can be recorded using PC based data
acquisition systems
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In addition, the PA bin computes the basic self and cross terms
between the voltage signals of the two polarizations, from which
the full Stokes parameters can be constructed
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The highest time resolution achievable is 128 microsec for the IA
mode and 512 microsec for the full Stokes PA mode
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These back-ends are available only for one sideband ( 16 MHz ) BW
and are connected to the upper sideband ( USB )
Web Designing
• What ???
• Why ???
• When ???
• Where ???
• How ???
Objectives :
• To provide maximum possible information
in a simple and efficient manner
• To make the contents interactive for the
visitors
• To provide clear understanding of the
working of the digital back-end
• To assemble the available information in a
planned and regulated manner
Data Accumulation
• Information about the workings of the various
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systems was acquired from the thesis works
done by many people and from the internal
reports of G.M.R.T.
Block Diagrams, schematics of various ICs, etc.
were taken from the maintenance files
Datasheets of ICs used were taken from the
internet
Images acquired from the respective incharge of
the system, printed images were scanned
Some block diagrams were constructed from
text
Methodology Employed
• The web page was divided into many frames
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and each frame was assigned some page
Some frames were kept stationary whereas
others were changed as per user input
Sidebar approach was incorporated for
navigation through the pages
Links were provided for moving from one page
to another
Site map was constructed to help navigation
A navigator was also constructed to facilitate
easy navigation from one part to other
Testing and Debugging
• Extensive testing of the link structure in the site
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was performed
www.browser-watch.com was referenced to find
out the most popular browsers and their
versions
Inter-browser compatibility was tested
The use of JavaScript and ActiveX contents was
kept minimum to reduce the loading time of the
pages
The Basic Structure
• The Top frame is an
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stationary frame giving the
logo of NCRA and the heading
of the system. Links for the
main page and site map have
been provided
The left side of the browser
window has been divided into
two frames which form the
sidebar navigation. The top
frame has information
pertaining to the respective
subsystem whereas the
bottom frame has general
information about the whole
system
The frames changes when
one moves from one
subsystem to another
The remaining portion of the
browser forms the ‘main’
frame
Links provided in the sidebar
open in the ‘main’ frame
Demonstration
• Just a minute
Future Scope
• Dynamic techniques like DHTML, XML,
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JavaScript, CSS, etc. can be used to make the
pages more interactive
The sidebar can be made with Flash to
incorporate dropdown menu styles to facilitate
more information in less spaces
Web pages for Software Back-end are to be
made
Scanned images used in the pages do not
provide good resolution. They can be replaced
with the original ones when available
Thank You