Transcript JAZiO presentation at Hot Interconnect 8 Symposium

1
JAZiO™ Incorporated
Digital Signal
Switching Technology
™
JAZiO
Incorporated
www.JAZiO.com
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JAZiO™ Incorporated
What is JAZiO Technology?
• A new method of interchip I/O switching
– At high data rate with low latency
– With low power
– At low cost
• Effectiveness is due to using
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Differential sensing with a single pin per bit
Built in timing
Look for change-of-data first
Transition detection
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JAZiO™ Incorporated
Traditional Signal Driving
(Peak Detection)
Next bit
time
One bit
time
tRF
tSU
tHD
Sharp Edges Cause:
Ground Bounce!
Cross Talk!
Ringing!
EMI!
High Power!
All information is
transmitted during
tRF (1/3 of bit time)
The rest of the bit time is
just wasted!
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JAZiO™ Incorporated
Pseudo Differential Signal Sensing
One bit
time
Next bit
time
 0.8V
VREF
Sensing
Level
Switching
Level
Sensing level about
1/3 of switching level
Large switching
levels cause:
The rest of the switching
level is just wasted!
Ground Bounce!
Cross Talk!
Ringing!
High Power!
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JAZiO™ Incorporated
JAZiO Solution
• JAZiO has invented a system which
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Achieves very high performance
Has edges which can take the whole bit time
Detects data value as soon as transition occurs
Uses differential sensing with low signal levels
Yet has only 1 pin per data signal
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JAZiO™ Incorporated
What’s the Secret? A Re-think
• For each data signal, there is either a change
or no-change from the previous bit time
• Traditional systems are good on no-change
but bad on change
• JAZiO looks for change first and then adjusts
if no-change occurs
• For JAZiO the decision binary is change or
no-change rather than high or low voltage
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JAZiO™ Incorporated
JAZiO Solution
VTR
Provide alternating Voltage/Timing
References switching at the data rate
VTR
Data
Input
1
2
3
4
One Bit
Time
VTR
Data
Input
5
6
7
Data is driven coincidentally
with Voltage/Timing References
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Next Bit
Time
8 different combinations of
VTR and Data Input
A
Dual Comparators are used
B
Steering
Logic
Data
Output
VTR
In cases 1 and 6 Comparator A makes a differential comparison
In cases 2 and 5 Comparator B makes a differential comparison
In the other four cases Data Input does not change
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JAZiO™ Incorporated
Steering Logic
The trick is to know how to select between
Comparators A and B and what to do
when Data Input does not change
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JAZiO™ Incorporated
Steering Logic
VTR
Data
Input
VTR
VTR
A
out
XOR
in
in
B
out
in
XOR
Receiver
Output
in
SL
VTR
SL
Latching
System
Latched
Output
VTR
• Generate Steering Logic signals (SL and SL)
• Use them with Data Output from previous Bit Time to
select between Comparators A and B
• Also use them for data latching
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JAZiO™ Incorporated
VTR
Data
Input
XOR
SL
Initialization
or
Receiver Enable
Data
Output
SL
XOR
VTR
Data
Input
55 Small Transistors Per Bit
No PLL/DLL Required
No die size penalty!!!
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JAZiO™ Incorporated
The receiver cell is:
22um x 55um
(Including routing channels)
The pad cell is:
70um x 80um
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JAZiO™ Incorporated
Time Domain
VTR
Data
Input
A
out
XOR
in
in
B
out
VTR
VTR
in
XOR
Data
Output
in
SL
VTR
SL
VTR
Data
Input
First
Look for
change
Determine nochange and
switch to
Comparator B
 0.5V
VTR
Decision is made in the Time Domain
rather voltage domain
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JAZiO™ Incorporated
JAZiO™ Receiver Operation
A
VTR
out
XOR-A
in
in
Data
Input
Data
Output
B
out
VTR
in
XOR-B
VTR
in
The
No-change
Cases
SL
VTR
SL
VTR
Initialize
Data
Input
VTR
VTR
SL
SL
CompA
CompB
XOR-A
XOR-B
Data
Output
0
1
1
0
0
1
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JAZiO™ Incorporated
Change /No Change Concept
Comp A
Data In
VTR
3
1
Data In
Comp A
THE
This band is based on
process mismatch (device
W, L, etc.), reflection or
overshoot (discontinuity,
GAP BECOMES
termination, inductance,
INFINITE etc.).
VTR
Change
No Change
• Case 1: Comp A amplifies the change and the data passes through the
Steering Logic
• Case 3: Comp A remains High past the point of change and the Data
Output retains the previous data
• The time gap is used by the steering logic to pass the change or block the
no-change from reaching the data output
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JAZiO™ Incorporated
The No-Change Case
VTR
A
out
in
XOR-A
SL
in
(High)
Data
Input
B
VTR
Data
Output
in
out
in
XOR-B
SL
Bit Time
Comparator A is selected
and as the differential on its
inputs disappears the output
remains high temporarily
Since Comparator A is selected its
high value causes Data Output
to remain high
However, Comparator B is
gaining a differential and its
Output becomes a solid high
But eventually the SLs will switch
causing the XORs to switch and
Comparator B will be selected
But!
The handoff from Comparator A to B
is smooth since both comparators
and Data Output are all high
After the handoff, Comparator B
is ready to make the next
differential comparison
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JAZiO™ Incorporated
Break-Before-Make
(Break-And-Remake)
1.8
Voltage (V)
xnora
Xnorb
vtr
1
Data Input
Data Output
0
4
5
Time (nS)
6
4nH Package
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JAZiO™ Incorporated
Data Skew at Receiver
Data
Input
1.25V/ns
+ 100mV
- 150mV
 500mV
Recommended
Skew band
VTR
Bit time = 0.5ns
Simulations show that width of Skew
Band can be up to 40% of bit time
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JAZiO™ Incorporated
SIGNALS
FROM
PADS
xorb
data_out 3
xora
xorb
xora
slb
data_out2
sl
xora
xorb
data_out 1
xorb
data_out 0
xora
4 Bit JAZiO Receiver From Test Chip
vtr
vtrb
data_in0
data_in1
data_in2
data_in3
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JAZiO™ Incorporated
16 JAZiO™ Receivers From Test Chip
Latch (latching at ¼ the data rate)
data_in15
data_in14
data_in13
data_in12
data_in11
data_in10
data_in7
vtr
vtrb
data_in8
data_in9
4-bit
JAZiO Receiver
data_in6
4-bit
JAZiO Receiver
data_in5
4-bit
JAZiO Receiver
data_in4
4-bit
JAZiO Receiver
data_in3
4 of 16
Serial to Parallel
data_in2
4 of 16
Serial to Parallel
data_in1
4 of 16
Serial to Parallel
data_in0
4 of 16
Serial to Parallel
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JAZiO™ Incorporated
Transition Detection
VH
Vref
Band
300mV
Diff Amp
Band
Transition Detection
• Higher frequency components, above the
maximum operating frequency, can be filtered
out at the receiver.
• Narrower voltage band for differential
amplifier operation (300mV).
• Self aligned data and VTRs shifts the steering
logic time, latching window and change/nochange gap in real time relative to Vcc,
temperature, manufacturing variations.
600mV
Diff Amp
Band
VL
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•
Pseudo Differential Peak Detection
Frequency components higher than the
maximum frequency need to be present at the
receiver (setup and hold time at VOH/VOL).
Wider voltage band for differential amplifier
operation is required (600mV).
Vref is a voltage average (Vcc, temperature and
manufacturing, and noise).
Clock is a time average based on PLL/DLL.
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JAZiO™ Incorporated
2nH Package & ESD Model
Low Pass
Filter
P-Ch Clamp
1nH
0.24
0.6pf
Lead frame
1nH
0.6pf
0.2
Pad
0.1pf
0.1pf
Bond Wire
200
1pf
N-Ch Clamp
Input
Protection
Resistor
Cint
To
Receiver
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JAZiO™ Incorporated
Simulation at 2Gb/s
At Pin
Voltage (V)
1.8
Data Output
Data Input
1
VTR
0
5
6
7
Voltage (V)
At
Receiver
Input
8
9
Time (nS)
Data Output
Data Input
1.8
1
VTR
0
5
6
7
8
9
Time (nS)
Middle of transmission line
Package inductance 2nH
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JAZiO™ Incorporated
Data Rate vs Slew Rate Comparison
10G
• Slower edges
• Lower switching
levels
• Reduced slew rate
Better
1G
100M
10M
0.5
1.0
1.5
2.0
2.5
Slew Rate (V/nS)
Higher Performance at Lower
Power with Higher Robustness
3.0
3.5
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JAZiO™ Incorporated
JAZiO Is Entirely Common-Mode
VTT
VTT
JAZiO
Signal
VTR
VTT
VTT
Signal
Pseudo Differential
VREF
1.
2.
3.
VSSQ noise between signal and VREF
VTT noise and/or VTT mismatch on either end
VREF impedance to Signal impedance mismatch
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JAZiO™ Incorporated
Applying JAZiO Technology
• JAZiO is the physical I/O layer only
– JAZiO provides no protocol
– Works with any protocol
– Like steel belted radial tires that work for Honda Civic,
Ferrari Sports Car, or Ford Explorer
• Easy to use
– No die size penalty
– No PLL/DLL or special semiconductor technology
– Low Power
• Can be used anywhere that fast switching or low
power is useful
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JAZiO™ Incorporated
JAZiO for DRAM
• JAZiO Technology can be applied to scaledup versions of existing protocols like DDR
or RDRAM
• Or new protocols can be developed to
match JAZiO’s low latency and high
bandwidth to reduce pins and increase
parallelism
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JAZiO™ Incorporated
1GHz CPU
with 2GHz
FSB & BSB
All scalable
to 2x
frequencies
L3
L3
L3
L3
CPU
CPU
CPU
BSB
CPU
16-Wide
MP Server
FSB
DRAM
CONTROLLER
2GHz Data Rate
Quad Processor
Module
I/O
Quad Processor
Module
2GHz
Interprocessor
Communication
(Scalable to 4GHz)
Quad Processor
Module
Quad Processor
Module
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JAZiO™ Incorporated
Notebook / Internet Appliance
SOC
DRAM
Power consumed in the memory interface is reduced due to low
switching levels of VTT=1.0v and VLOW=0.5v
Pavg = K•Dv•VTT
K a (Cf+1/Rt)
Therefore
Power Ratio = (0.5v•1)/(0.8v•1.8) 1/3
When compared to existing pseudo differential with VTT=1.8v, VLOW=1.0v,
similar load capacitance, operating frequency and termination resistance
Small swing and slower transition time reduces
EMI allowing it to meet FCC limits for radiation
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JAZiO™ Incorporated
How Can JAZiO Be Used?
• JAZiO is “essentially” an Open Standard
• All technology is publicly visible w/o NDA
• Anyone can see it, study it, simulate it, design it in,
build test chips, build prototypes, etc
• Just don’t sell products without licensing it
• A JAZiO demonstration chip has been designed by
Micro Magic, Inc – a JAZiO Design Services partner
(www.micromagic.com)
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JAZiO™ Incorporated
Conclusion
• JAZiO uses lower levels and slower edges
• Achieves high performance, low power, high
robustness
• JAZiO technology is fundamentally different from
traditional methods
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Transition Detection rather than Peak Detection
Time domain rather than voltage domain
Look for change first
Change vs No-change rather than High or Low
• JAZiO is available to everyone at low cost and applies
to any application