Transcript Introduction to Data Conversion

Introduction to Data Conversion
EE174 – SJSU
Tan Nguyen
Vocabulary
• ADC (Analog-to-Digital Converter): converts an analog signal (voltage/current) to a digital value
• DAC (Digital-to-Analog Converter): converts a digital value to an analog value (voltage/current)
• Sample period: for ADC, time between each conversion
• Typically, samples are taken at a fixed rate
• Full Scale output (VFS) and Reference voltage (Vref): Analog signal varies between 0 and Vref, or between
+/-Vref . Note: VFS = Vref – 1LSB.
• Resolution: Number of bits used for conversion (8 bits, 10 bits, 12 bits, 16 bits, etc).
• Conversion Time: The time it takes for an analog-to-digital conversion
• Quantization is the process of converting a continuous range of values into a finite range of discreet
values. This is a function of ADC, which create a series of digital values to represent the original analog
signal.
• Differential Nonlinearity (DNL) error is the difference between an actual step width (for an ADC) or
step height (for a DAC) and the ideal value of 1 LSB.
• Integral Nonlinearity (INL) error is the deviation of the values on the actual transfer function from a
straight line.
• Effective Number Of Bits (ENOB) is a measure of the dynamic performance of an ADC.
Data Conversion System
• Real world signals are analog signals continuous time & amplitude (temp, pressure, position, sound, light, speed, etc).
• DSP can only process digital signals which are discrete time and discrete amplitude.
 Digital data conversion system requires ADC and DAC.
• ADC process utilizes sampling and quantization of the continuous analog signal.
• ADC converts an input analog value to an output digital representation.
• ADC is operated at a rate of fS samples per second. Anti-alias filter is used to
avoid any aliasing phenomena.
• ADCs usually require the input be held constant during the conversion process,
indicating that the ADC must be preceded by an Sample-and-Hold Amplifier
(SHA) to freeze the band-limited signal just prior to each conversion.
ADC is commonly needed,
most microcontrollers has
built-in ADC unit.
•
•
•
•
The DAC reverses the ADC process. Signal reconstruction from sampled data.
The digital data is processed by a microprocessor and output to a DAC.
DAC is usually operated at the same rate fS as the ADC
When the application demands, it is equipped with appropriate circuitry to
remove any output glitches arising in connection with input code changes. The
resulting staircase-like signal is finally passed through a smoothing filter to ease
the effects of quantization noise.
Illustration of ADC Process
There are two related steps in A-to-D conversion:
Sampling and holding:
The analogue signal is extracted, usually at regularly spaced time instants.
The samples have real values.
Quantization and Encoding:
The samples are quantized to discrete levels.
Each sample is represented as a digital value.
Nyquist-Shannon Sampling Theorem
The Nyquist-Shannon Sampling Theorem states that the sampling rate for exact recovery of a signal composed of a
sum of sinusoids is larger than twice the maximum frequency of the signal.
This rate is called the Nyquist sampling rate fNyquist.
fs > fNyquist = 2fmax
Example 1: Given the signal v(t) = 7 + 5cos(2π440t) + 3sin(2π880t) , what is the proper sampling rate?
Solution: The proper sampling rate fs > fNyquist= 2(880)=1760 Hz.
Example 2: Given the signal v(t) = 2sin(180πt) = 2sin(2π90t) is sampled at fs1 = 1000 Hz and fs2 = 95 Hz , what signal
can be recovered after sampled?
Solution:
For fs1 = 1000 Hz  v1[n] = 2sin(2πn 90/1000) = 2sin(2πn(0.09)) = 2sin(0.18πn)
Recovering signal: vr1(t) = 2sin(0.18π tx1000) = 2sin(180πt) = 2sin(2π 90t)  Signal recovered
For fs2 = 95 Hz  vr2[n] = 2sin(2πn 90/95) = 2sin(πn(1.9)) = 2sin(πn(2 – 0.1)) = 2sin(πn( – 0.1)) = – 2sin(0.1πn)
Recovering signal: vr2(t) = – 2sin(0.1πtx95) = – 2sin(9.5πt) = – 2sin(2π4.75t)  Signal is not recovered
 Sampling rate less than Nyquist rate results in original signal is not recovered known as aliasing phenomena
Sampling Theorem
A sinusoid signal of 90 cycle/second is sampled at
fs = 1000 samples/second. The wave has a
frequency of 0.09 of the sampling rate:
f = 0.09 x fs = 0.09 x 1000 = 90 Hz.
Equivalently, there are 1000/90 = 11.1 samples
taken over a complete cycle of the sinusoid.
 This is proper sampling since the samples
represent accurately the sinusoid because there
is no other sinusoid that can produce the same
samples.
Now, if sampling fs = 95 samples/second
f = 0.95 x fs or there are 1.05 samples per sin wave cycle.
Clearly, this is an improper sampling of the signal because
another sine wave can produce the same samples.
The original sine misrepresents itself as another sine. This
phenomenon is called aliasing.
Why 44.1 kHz for Audio CDs?
Sound is audible in 20 Hz to 20 kHz range:
fmax = 20 kHz and the Nyquist rate 2 fmax = 40 kHz
What is the extra 10% of the bandwidth used?
Rolloff from passband to stopband in the magnitude response of the anti-aliasing filter
44 kHz makes sense. Why 44.1 kHz?
At the time the choice was made, only recorders capable of storing such high rates were VCRs.
NTSC: 490 lines/frame, 3 samples/line, 30 frames/s = 44100 samples/s
PAL: 588 lines/frame, 3 samples/line, 25 frames/s = 44100 samples/s
CD-ROM Mode 1 = 2,048 bytes/block,
CD-ROM Mode 2 = 2,336/bytes/block,
CD data transfer rate of 75 blocks per second by 60 seconds by the minute size of disc.
For example, a 80 minute disc written in CD-ROM Mode 1 format:
Total CD storage space = 2048 bytes/block x 75 blocks/second x 60 seconds x 80 minutes = 737,280,000
bytes or 800MB.
Analog-to-Digital Converter (ADC)
• ADC converts an input analog value to an output digital representation.
• ADC is operated at a rate of fS samples per second. Anti-alias filter is used
to avoid any aliasing phenomena.
• ADCs usually require the input be held constant during the conversion
process, indicating that the ADC must be preceded by an Sample-andHold Amplifier (SHA) to freeze the band-limited signal just prior to each
conversion.
ADC Process
Sampling & Hold
• Measuring analog signals
at uniform time intervals
• Ideally twice as fast as what
we are sampling
Continuous Signal
• Digital system works with
discrete states
• Taking samples from each
location
• Reflects sampled and hold
signal
• Digital approximation
t
ADC Process
Sampling & Hold
• Measuring analog signals at
uniform time intervals
• Ideally > twice as fast as what we
are sampling
• Digital system works with
discrete states
• Taking samples from each
location
• Reflects sampled and hold
signal
• Digital approximation
t
ADC Process
Sampling & Hold
• Measuring analog signals at
uniform time intervals
• Ideally > twice as fast as what we
are sampling
• Digital system works with discrete
states
• Taking a sample from each
location
t
• Reflects sampled and
hold signal
• Digital approximation
ADC Process
Sampling & Hold
• Measuring analog signals at
uniform time intervals
• Ideally > twice as fast as what we
are sampling
• Digital system works with discrete
states
• Taking samples from each
location
• Reflects sampled and hold signal
• Digital approximation
t
Sample and hold: The output only
changes at periodic instants of time. The
independent variable now takes values
in a discrete set
ADC Process
Quantization & Coding
Quantization error
• Use original analog signal
• Apply 2 bit coding
• Use original analog signal
• Apply 3 bit coding
Better representation of input information with additional bits
• Quantizing: Partitioning
the reference signal range
into a number of discrete
quanta, then matching
the input signal to the
correct quantum.
• Encoding: Assigning a
unique digital code to
each quantum, then
allocating the digital code
to the input signal.
A 5 kHz Sine Wave sampled by a 3-bit versus a 16-bit ADC
Improve the accuracy in ADC
• Increase the sampling rate which increases the maximum frequency that can be measured.
• Increase the resolution which improves the accuracy in measuring the amplitude of the analog signal.
ADC Characteristics
• An ideal ADC:
Output
code
For Vref = 5V, step size (1LSB) = 5V/256 = 0.0195V
• Accepts analog input in the form of either voltage or current
• Produces digital output either in serial or parallel form
N = # of bits
2N − 1
VFS= Full scale output = Vref – 1 LSB = Vref 2N
V
𝑸 = min. resolvable input  1 LSB = 2ref
N
• Resolution:
• Resolution is the smallest input voltage change a digitizer can
capture
• Resolution of a N-bit ADC is defined as
Q=
Vref
2N
• ADC Equations:
where Vref = (Vref+ - Vref-).
If Vref- = 0 V, Vref = Vref+
Given Vin = input voltage, Vref = VFS, N = number of bits of precision.
V
output_code
Output_code = V in x 2N or Vin =
x Vref
2N
ref
Quantization Noise Model
• When an ADC converts a continuous signal into a discrete digital representation, there is a range of input values
that produces the same output. That range is called quantum (Q) and is equivalent to the Least Significant Bit
(LSB). The difference between input and output is called the quantization error.
• Therefore, the quantization error can be between ±Q/2.
Ideal ADC transfer
function
Ideal 3-bit ADC Quantization Noise
• Any value of the error is equally likely, so it has a
uniform distribution ranging from −Q/2 to +Q/2.
Then, this error can be considered a quantization
noise with RMS:
Signal-Noise Ratio (SNR) relates to N-bits in digital presentation
Assuming an input sinusoidal with peak-to-peak amplitude Vref, where Vref is the reference voltage of an N-bit ADC
(therefore, occupying the full-scale of the ADC), its RMS value is
To calculate the Signal-Noise Ratio, we divide the RMS of the input signal by the RMS of the quantization noise:
SNR = 6.02 x N + 1.76 (dB)
This SNR equation generalizes to any system using a digital representation.
ADC : Parameters
Number of bits N: The higher is the number of bits, the more precise is the digital output.
Quantisation error Eq: The average difference between the analogue input and the quantized value. The
quantization error of an ideal ADC is half of the step size.
Sample time Tsample: A sampling capacitor must be charged for a duration of Tsample before conversion taking place.
Conversion time Tconv: Time taken to convert the voltage on the sampling capacitor to a digital output.
Examples
1) Given Vref = 10V, N=12, and Vin = 9V. Find: (a) the resolution Q (1 LSB), (b) the output_code, (c) the quantization
noise vqn, (d) the SNR.
Solutions:
(a) A 12 bit ADC has a resolution of 212 = 4,096. Therefore, our best resolution is 1 part out of 4,096, or 0.0244% of
the full scale or 10V / 212 = 2.44 mV
V
9
(b) Output_ code = V in x 2N = 10 x 4096 = 368610 = 0xE66
FS
(c) vqn =
= 0.704 mV
(d) SNR = 6.02 x N + 1.76 = 6.02 x 12 + 1.76 = 74 dB
2) Given an input voltage Vin = 9V with Vref = 10V. Determine minimum bits (N) would be required to have less than ±
0.5% quantization error?
Q
V
Known: Absolute quantization error |QE| (in mV ) = ± . And, Q = ref
.
2
2N
Solution:
|𝑄𝐸|
Q
=
0.5%
=
0.005

|QE|
=
9000
mV
x
0.005
=
45
mV
=
9000 𝑚𝑉
2  Q = 90 mV/bit (LSB)
V
N = Vref = 10,000 mV ≈ 111
Q = 90 mV/bit = 2ref

2
N
90 mV
90 mV
log 111
N=
≈ 6.8  so minimum N = 8 because 7-bit DAC not available. Note: Higher N will also work but added
log 2
cost.
Examples
3) Given Vref = 10V, and a 10-bit A/D output code is 0x12A.
a) What is the ADC input voltage?
b) If the input voltage is Vin = 2.915 V, what is the output code?
c) What is the input voltage range that yield an output code of 0x005?
Solution:
1 LSB = Q = 10V / 210 = 0.00976 V = 9.76 mV  Q/2 = 4.88 mV
a) Vin = output_code / 2N * Vref = (0x12A) / 210 x 5 V = 298/1024 x 10 V
= 2.91015 V = 2910.15 mV (ADC Vin)
b) For the output code 0x12A, the input voltage range is 2910.15 ± Q/2 or
2905.27 mV < V0x12A < 2915.03 mV
So for Vin = 2.915 V the out put code is also 0x12A
c) The ideal input voltage to produce output code 5 is
V0x005 = 5 x 9.76 mV = 48.8 mV
The range for output code 0x005 is 48.8 ± 4.88 mV or
43.92 mV < V0x005 < 53.68 mV
Digital-to-Analog Converter (DAC)
• The digital data is processed by a microprocessor and output to a DAC.
• DAC is usually operated at the same rate fS as the ADC
• When the application demands, it is equipped with appropriate circuitry to remove any
output glitches arising in connection with input code changes. The resulting staircase-like
signal is finally passed through a smoothing filter to ease the effects of quantization noise.
DAC Characteristics
• An ideal DAC:
• Accepts digital input b1- bN
• Produces either analog output voltage or current
N = # of bits
V
Q = min. step size  1 LSB = 2ref
N
• LSB and MSB:
• LSB and MSB of a N-bit DAC is defined as
LSB =
Vref
2N
where Vref = (Vref+ - Vref-)
V
MSB = 2ref
If Vref- = 0 V, Vref = Vref+
V
N = log2 Qref  Resolution
• DAC Equations:
Given Vout = output voltage, Vref, N = number of bits of precision
V
input_code
Input_code = Vout x 2N or Vout =
x Vref
N
2
ref
V
Vout_max= Vref – Q = Vref – 1 LSB = Vref ( 1 – 2ref
N)
Example DAC Computations
1) Given N=3, Vref= 1.6V.
a) Find the LSB or Q value.
b) Find the MSB value.
c) Find the maximum output Vout_max
d) Find the output value Vout when the input code = 1012
Solution:
V
1.6 V
a) LSB = Q = 2ref
=
3
8 = 0.2V
V
1.6 V
b) MSB = ref =
= 0.8V
2
2
c) Vout_max = Vref – Q = 1.6 – 0.2 = 1.4V
d) Vout = Q (b1x22 + b2x21 + b3x20) = 0.2V (1x22 + 0x21 + 1x20) = 0.2V x 5 = 1V
2) Given Vref = 4V and an 8-bit DAC.
a) If the output voltage is 2.345 V, what is the DAC input code?
b) If the output voltage is 2.357 V, what is the DAC input code?
c) What conclusion can you draw from a) and b)?
Solution:
V
2.345
a) Input code = V in x 2N = 4 x 28 = 150.08 or 15010 = 0x96 (DAC input code)
ref
Vin
2.357
b) Input code = V x 2N = 4 x 28 = 150.85 or 15010 = 0x96 (DAC input code)
ref
c) Both output voltage differences are in the range of input_code of 0x96.
Example DAC Computations
3) A design requires step size or LSB = 0.002 V and the reference voltage Vref = 1.6V.
a) Determine the minimum resolution N.
b) Find the MSB value.
c) Find the maximum output Vout_max
d) Find the input code for the output voltage Vout = 0.799V
Solution:
V
1.6 V
a) N = log2 Qref = log2 0.002 = log2(800) = 9.64  N = 10 is minimum requirement
V
1.6 V
b) MSB = 2ref = 2 = 0.8V
c) Vout_max = VFS – Q = 1.6 – 0.002 = 1.598V
V
0.799
d) Input_code = Vout x 2N = 1.6 x 1024 = 511.36  Input_code = 51210 or 0x800
ref
Some Data Sheet Examples
References:
http://www.ni.com/white-paper/4806/en/
http://inst.eecs.berkeley.edu/~ee247/fa10/files07/lectures/L11_2_f10.pdf
http://194.81.104.27/~brian/DSP/ADC_notes.pdf
http://ume.gatech.edu/mechatronics_course/ADC_F08.pdf
ume.gatech.edu/mechatronics_course/ADC_F10.pptx
http://astro.temple.edu/~silage/Chapter8MS.pdf
http://www.embedded.com/design/configurable-systems/4025078/Understanding-analog-to-digital-converterspecifications
ume.gatech.edu/mechatronics_course/ADC_F12.pptx
http://www.elin.ttu.ee/~olev/lect2.pdf
http://my.ece.msstate.edu/faculty/reese/ece3724_pic16/lectures/adcdac.pdf
http://www.mediacollege.com/glossary/q/quantization.html
http://www.ti.com/lit/an/slaa013/slaa013.pdf
http://www.ti.com/europe/downloads/Key%20Parameters.pdf
https://courses.engr.illinois.edu/ece110/content/courseNotes/files/?samplingAndQuantization
http://www.onmyphd.com/?p=quantization.noise.snr
http://masteringelectronicsdesign.com/an-adc-and-dac-least-significant-bit-lsb/