Transcript System structure

Non-BELLE applications
EDET DH80k TEM camera:
System overview
20th international workshop on DEPFET Detectors
Seeon monastery
11.5.2015
Johannes Treis MPI Halbleiterlabor
Contents
• System design philosophy
• Challenges
• System structure
• System components
• ASM
• Brick support
• Patch Panel
• Summary & Outlook
Johannes Treis / Halbleiterlabor der MPG
System design philosophy
Concept:
Benefits:
• Detector FPA consisting of 4 individual, independent
modules ("tiles") .
• Easy to duplicate
• Each tile has its own set of peripheral components:
• Easy refurbishment of broken parts, only reversible
connections
• Quadrant electronics
• Reduced instrument downtime
• Cable harness
• Easy subsystem operation with reduced FPA size
• Vacuum feedthrough
• Maximum modular approach:
• Modules are identical, no specialized
components
• Modules are exchangeable and interchangeable
• Easy replacement and refurbishment
• Minimal number of peripheral components
• "Stand alone" operation for every module
• Adopt same architecture for (later) DH1K camera
Johannes Treis / Halbleiterlabor der MPG
Challenges I
Gradient 46°C
500
Thermomechanical:
400
0
(30
• Thermal challenge: Prevent formation of
too-large temperature gradients over
detector area
7,7
300
Row #
• Thin detector substrate of all-silicon module
mm and 50 mm)
23
31
200
38
46
100
• Mechanical challenge: Protect detector in
sensitive parts (e.g. corners) from
mechanical stress due e.g. CTE mismatch
100
200
300
400
500
Column #
Gradient 41°C
• Provide heatsink for thermal stabilizatio0n
of both detector modules and module
individual electronics inside vacuum vessel
500
400
0
3,4
6,8
10
300
Row #
• Design must be robust against
temperatures and mechanical stresses
introduced during foreseen annealing
procedure
15
14
17
20
24
200
27
30
34
37
41
100
100
200
300
Column #
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400
500
Challenges II
Electromechanical:
Data rate:
• Width of electrical vacuum feedthrough limited
• DH80K takes bursts of 100 frames at 80 kHz
• Detachable connection between various
components (rules out direct soldering of flex)
• Compact and reliable high pincount connectors for
most inter-component joints
• 13 ms / frame
• 1.3 ms per burst
• Burst frequency ~ 10 ms
• Wire bonds can not be completely avoided
• Duty cycle ~ 10:1
• EDET DCD digitizes data from 512 x 512 pixels per
quadrant with 8 bit resolution
Electrical:
• Reduce pincount as much as possible
• 262 kByte / Frame
• Large supply currents at low voltages
• 26.2 MByte / burst
• High number of supply and sense lines
• 2.6 GByte / s
• Large number of data transmission lines
• Full scale system consists of 4 tile modules
• Total data rate ~ 10.5 GByte /s
• Data reduction / zero suppression difficult
Johannes Treis / Halbleiterlabor der MPG
System structure
System components:
• ASM: All-Silicon module
• Brick support: Mechanical and thermal support for
ASM and interface to main heatsink
• Patch panel: Wire bond adapter and local power
conditioning and housekeeping circuitry
• Vacuum interconnect: Flexlead for vacuum
feedthrough of all digital and analog signals &
supplies
• Module interface circuitry: Interface to readout
system controllers, power conditioning
Johannes Treis / Halbleiterlabor der MPG
System structure
FPA stack:
• 4 tiles per detector FPA
• Mounted (clamped) on common
heatsink attached to cold head of
cooler
• Cooler cools away dissipated power
and stabilized assembly to required
operating temperature
• Modular approach:
• Individual support circuitry on
Patch panel
• Individual cable harness
• Individual vacuum feedthrough
• Modules can independently be attached and
detached from common heatsink
• Reversible mount in case of module damage
or refurbishment of worn out modules
• Requires each module to have an individual
thermomechanical support (BRICK support)
Johannes Treis / Halbleiterlabor der MPG
System structure
Insertion:
Top view:
• Insertion fo comlete FPA stack from below
• Feedthrough flanges integrated on
baseplate flange
• No cable mounting from top required after
insertion
• Displacement wrt. ASM accommodated by
"Double L" shaped patchpanel
Johannes Treis / Halbleiterlabor der MPG
System structure
"Double-L" shaped patch panel:
• Support multi-pin connector
• Support buffer capacitors in bonding
section close to conection to ASM
• Support circuitry for
• Driving the LVDS signals from
the DMC over the VIC to the
outside
• Local regulation of DCD and
DMC supply voltages
• Level out displacement between ASM
edge and VIC position on baseplate
flange
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System structure
Vacuum interface connect (VIC):
• Potted PCB with connector on both
sides with UVH compatible adhesive
• Tested & qualified for FSP
• Homogeneous impedance
• For optimum digital signal quality
• Modular and exchangeable
• No active components
Johannes Treis / Halbleiterlabor der MPG
System structure
CAD views
Johannes Treis / Halbleiterlabor der MPG
System structure
Module structure:
• Each module operates as an independent
subdetector
• Synchronized by central sequencer
• Power generation & conditioning in-module:
• On MIC: DEPFET power and switcher
voltages
• On Patchpanel: Drop-Critical DMC and DCD
voltages
• "Local" sensing on patchpanel to
compensate for on-module voltage drops
• Saves numerous feedthrough and sense
lines
• Configuration, control and housekeeping for
module via the same interface
• Simple, standardized external power supplies
• Simple vacuum feedthrough optimized for digital
data transmission
Johannes Treis / Halbleiterlabor der MPG
System structure
Module Interface circuitry (MIC) :
• Peripheral interconnect based on simple FPGA I/O module
• EDET specific daughter card (EDC)
• Communication & setup using TCP/IP stack
• JTAG interface for DCD / DMC / Switcher configuration is provided by an (optional) FPGA on Microcontroller the EDC
• Filters for primary (raw) power, conditioning for Switcher & DEPFET voltages
• Buffer for LVDS data from DMCs (32 diff. pairs)
• Receiver for synchronization signal from main sequencer (clock)
Johannes Treis / Halbleiterlabor der MPG
System structure
DAQ Concept:
• Data from 32 LVDS links per Module is delivered to
distribution panel on DAQ rack
• Redistributed to Data Capture Cards (DCCs) for assembly
of frames and sending to Switch/Storage system
• Single power supply or modul-individual "raw" power
supplies per detector module
• One sequencer module per detector system provides for
synchronized operation of subdetectors
• Configuration & control of components via Control PC
using TCP/IP connection(s)
Johannes Treis / Halbleiterlabor der MPG
System structure
Alternative MIC Concept:
• Peripheral interconnect based on Data wrapper FPGA module
• Project-specific daughter card (EDC, to be developed)
• Communication & setup using TCP/IP stack
• Data transfer via (multiple) GBit Ethernet interface directly to Switch
Johannes Treis / Halbleiterlabor der MPG
System structure
Alternative Concept:
• Foresee module-individual data wrapper FPGA module
• Transfer module data directly over GBit Ethernet link(s)
and Switch to storage device
• Data rate here is 2.6 GByte /s (21 GBit /s)
• More complex assembly of frame data
• Less components in total, higher degree of modularity
Johannes Treis / Halbleiterlabor der MPG
ASM
•
Configuration and
control structure
similar to PXD-9 ASM
•
Specific ASICS
•
Application-specific
DCD
•
DMC as data Buffer
Chip
JTAG
Bias contacts
Switcher Bank
Pixel array
30.7 x 30. 7 mm2
Bondpads
for DCD / DMC
data & supplies
DMC array
DCD array
Chip size
~ 50 x 38 mm2
(EDET specific DCD)
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Test pads
(removed after
met. 1 testing)
BRICK support
Concept:
• Need support under entire frame
• Issues have been investigated using FEM
• Thick material to get rid of the heat, lower thermal
gradients
• Results for stress analysis and partially
also thermal analysis depend strongly on
fixture and clamping methods
• CTE match close to optimum to reduce stress
ASM glued to Brick support
• Opening below (cavity) to provide beamdump
• Robust structure
• Materials under investigation:
• Polysilicon:
• Expensive, brittle, difficult to
machine,
• Optimum CTE match and thermal
performance
• Titanium:
• Reduced thermal performance,
easier to machine, less expensive
Bevelled aproach
for beam dump
• Higher stress and thermal gradients
due to non-optimum CTE match and
thermal conductivity
Johannes Treis / Halbleiterlabor der MPG
Thermal support over full backside area
equal reference temperature of 0°
BRICK support
Polysilicon
Titanium
Comparison:
• Equal color scale span
• Corrected for individual offset temperature
• Difference in temperature gradient ~ 2°C
• 25% higher leakage current gradient
• Higher offset (not significant)
• Significant temperature offset for R/O chips
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BRICK support
Curing stress Titanium:
• max. von Mises Stress 434 MPa
• Highest stress values in support
area
• High stress also in transition
region from thin to thick silicon
• Max. stress here is 240 MPa
Johannes Treis / Halbleiterlabor der MPG
BRICK support
Curing stress Polysilicon:
• max. von Mises Stress in thin
area is 17.8 MPa
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Patch panel bonding section
Concept:
• Depth milling process for "stepped" access to inner layers
• Especially important for contacts in region of high density
interconnects (LVDS fanout)
• Saves huge number of vias
• Embedding of trace pairs between fixed potential layers
possible
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Patch panel bonding section
Population of components on
top layer
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Patch panel circuit section
Main problem:
DCD power2):
• Large supply currents for DCD / DMC
• DVDD:
2.2 V, 1.5 A
• Substantial resistance of supply lines
• AVDD:
1.9 V, 5 A
• Strong variations of currents depending of operation state
• VRefin5):
1 V, 800 mA
• Sense lines required!
• VAmpLo5):
300 / 500 mV, 1.5 A, Current sink (!)
• Maximum granularity of system: Supplies in 4 groups of 2
DCD / DMC pairs each
2)
8 Devices, 4 groups of 2 each
5)
VRefin, VAmpLo individually adjustable
• Actual granularity tbd.
• Space is not critical, so local regulation is suggested
DMC power3):
• Using low noise / high current LDO regulators
• VCore:
1.1 V, 4 A
• LDO power dissipation needs to be taken care of (thermal
management)
• VI/O:
1.8 V, 4 A
3)
Estimated values
• Housekeeping of current and voltage (and temperature)
required
• Power supply prototype for use with DCD / DHP or DCD
DMC modules has been designed
Johannes Treis / Halbleiterlabor der MPG
Patch panel circuit section
Positive supplies:
• Generate Power from single
"raw" supply
• AVDD / DVDD / VRef
• DMC voltages
• Adjustable Voltage for Vref
• Real hi and lo side (2 wire)
sense
• Requires use of difference
amplifier due to nonzero
resistance of sense lines
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Patch panel circuit section
Positive current sink:
• VAMPLO
• Generate Power from AVDD
supply using bootstrapped
negative LDO
• Adjustable Voltage
• Real hi and lo side (2 wire)
sense
• Difference amplifier needs to
be referenced to AVDD
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Patch panel circuit section
Housekeeping:
• Monitoring of both current
and voltage
• Optionally, voltage applied to
the load can be monitored
• Controlled via I2C bus
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Patch panel circuit section
Thermal management:
• Dropout voltage low, but raw supply needs to
accomodate all voltages
• High currents -> relatively high power
dissipation in regulators
• Thermal management is an issue
• Using solid copper inlays for thermal
stabilization and optimization of thermal
coupling to heatsink
• Use Semi-Flex PCB technology to improve
connection between Circuit section and
bonding section of Patch Panel
Images: courtesy Häusermann
Johannes Treis / Halbleiterlabor der MPG
Summary
Status:
• Design of camera system consolidates
• Progress in conceptual, mechanical and
electrical system design
• Prototyping of critical circuit components
• Thermal dummy tests to verify critical
thermal and machanical aspects of design
Open questions:
• Annealing?
• BRICK support material
• Form factor for MIC
Johannes Treis / Halbleiterlabor der MPG