Transcript Digital Circuit Design for Minimum Transient Energy and a Linear

Digital Circuit Design for
Minimum Transient Energy
Vishwani D. Agrawal
Circuits and Systems Research Lab, Agere Systems (Bell Labs, Lucent
Tech.)
Murray Hill, NJ 07974
[email protected]
http://cm.bell-labs.com/cm/cs/who/va
Research Collaborators:
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M. L. Bushnell, Rutgers University
R. Ramadoss, Lucent Microelectronics
G. Parthasarathy, UC Santa Barbara
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Power in a CMOS Gate
VDD = 5V
IDD
Ground
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Motivation
• Low power applications
• Remote systems (e.g., satellite)
• Portable systems (e.g., mobile phone)
• Methods of low power design
• Reduced supply voltage
• Adiabatic switching
• Clock suppression
• Logic design for reduced activity
• Reduce Hazards (40% in arithmetic logic)
• Software techniques
• Reference: Chandrakasan and Brodersen
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Problem Statement
• Design a digital circuit for minimum
transient energy consumption by
eliminating hazards
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Main Result: Theorem 1
• For correct operation with minimum
energy consumption, a Boolean gate
must produce no more than one
event per transition
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Theorem 2
• Given that events occur at the input of a
gate (inertial delay = d ) at times t1 < . .
. < tn , the number of events at the gate
output cannot exceed
tn – t1
min ( n , 1 + -------d
)
tn - t1 + d
t1
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t2
t3
d
tn
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tn +
time
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Minimum Transient Design
• Minimum transient energy condition
for a Boolean gate:
| t i - tj | <
d
Where ti and tj are arrival times of input
events and d is the inertial delay of gate
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Balanced Delay Method
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•
•
All input events arrive simultaneously
Overall circuit delay not increased
Delay buffers may have to be inserted
4?
1
1
1
1
1
1
1
3
1
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Hazard Filter Method
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•
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Gate delay is made greater than maximum input
path delay difference
No delay buffers needed (least transient energy)
Overall circuit delay may increase
2
1
1
1
1
1?
3?
1
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1
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2
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Linear Program
• Variables: gate and buffer delays
• Objective: minimize number of
•
•
•
buffers
Subject to: overall circuit delay
Subject to: minimum transient
condition for multi-input gates
AMPL, MINOS 5.5 (Fourer, Gay and
Kernighan)
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Variables: Full Adder add1b
0
0
0
0
0
1
1
1
0
0
1
0
0
0
1
1
1
0
0
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1
0
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Objective Function
• Ideal: minimize the number of non•
zero delay buffers
Actual: sum of buffer delays
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Specify Critical Path Delay
0
0
0
0
0
1
1
1
0
0
1
0
0
0
1
1
1
1
0
0
0
1
Sum of delays on critical path _< maxdel
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Multi-Input Gate Condition
d1
0
0
0
1
d
d
1
0
0
1
0
1
d
d2
d1 - d2 <
_d
d2 - d1 <
_d
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AMPL Solution: maxdel = 6
1
2
1
1
1
2
1
1
1
2
2
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AMPL Solution: maxdel = 7
3
1
1
1
2
1
1
2
1
2
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AMPL Solution: maxdel_> 11
5
1
1
1
2
3
1
3
4
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Power Estimates for add1b
Power* with respect to Ref.
No.
maxdel
of
Ref: model del.
Ref: unit del.
buf.
Peak
Ave.
Peak
Ave.
6
2
0.60
0.89
0.60
0.90
7
1
0.56
0.85
0.56
0.86
_
>11
0
0.52
0.80
0.52
0.81
* Hsiao et al., ICCAD-97
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VDD
Open at t = 0
Large C
V
Circuit
Energy, E(t)
Power Calculation in Spice
t
Ground
1 C VDD 2 - 1-- C V 2 ~ C VDD ( VDD - V
E(t) = -)
2
2
Ref.: M. Shoji, CMOS Digital Circuit Technology, Prentice Hall, 1988, p. 172.
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Power Dissipation of ALU4
Energy in nanojoules
7
1 micron CMOS, 57 gates, 14 PI, 8 PO
100 random vectors simulated in Spice
6
5
Original ALU
delay ~ 3.5ns
4
3
Minimum energy ALU
delay ~ 10ns
2
1
0
0.0
0.5
1.0
1.5
2.0
microseconds
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Signal Amplitude, Volts
F0 Output of ALU4
Original ALU, delay = 7 units (~3.5ns)
5
0
Minimum energy ALU, delay = 21 units (~10ns)
5
0
0
40
80
120
160
nanoseconds
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Some Comments
• J. Bentley: Path enumeration may be
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•
avoided by retiming type algorithms;
Leiserson and Saxe, PhD theses
M. Yannakakis: Use ellipsoid method
if you can verify a solution in linear
time; also try partitioning approach
M. Wright: Use ILP
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References
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E. Jacobs and M. Berkelaar, “Using Gate Sizing to Reduce
Glitch Power,” Proc. ProRISC/IEEE Workshop on Circuits,
Systems and Signal Processing, Nov. 1996, pp. 183-188;
also Int. Workshop on Logic Synthesis, May 1997.
V. D. Agrawal, “Low-Power Design by Hazard Filtering,”
Proc. 10th Int. Conf. VLSI Design, Jan. 1997, pp. 193-197.
V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R.
Ramadoss, “Digital Circuit Design for Minimum Transient
Energy and a Linear Programming Method,” Proc. 12th Int.
Conf. VLSI Design, Jan. 1999, pp. 434-439.
Last two papers are available at website http://cm.belllabs.com/cm/cs/who/va
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Conclusion
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•
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Linear programming gives optimum design
Analysis may reduce the number of constraints
Technique can be applied to partitioned circuit
An alternative min-flow formulation avoids path
enumeration (approximate method)
Transistor-sizing problem can be reformulated for
area, delay and power reduction
Glitch-free circuits have better timing properties
Applications to CPU time reduction in programs
and in project management for reduced cost
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