Transcript Results from Measurements Performed on 27 Oct. at up to

Status and Preliminary Testing of the
Hyper
Bus Fault
Detector
New
Work done by
CP section 10-12.2008
Based on Slides from Knud DAHLERUP-PETERSEN
Architectural Design by Reiner DENZ
Analysis by Zinur CHARIFOULLINE
Both functional aspects of the new
bus fault detector have been
tested:
❖( Preliminary
Bus Splice Quality Characterization
Nano Ohm Meter Function)
❖ Voltage Signal Noise Reduction Integration Hierarchy
❖
❖
❖
❖
❖
Differential Analog Bandwidth: 0-200 Hz (tested at 1 kHz)
24bit ∑∆ ADC (modulator frequency: 32768 Hz)
Hardware (in QPS) 24bit ∑∆ ADC integration period: 187 mS (5.35 Hz)
Firmware (in QPS) moving rectangular integration:
18.9 S (101 samples)
Software (in CCC) DC integration time: typically > 10 minutes
(this is what counts!)
❖ Feasibility of nΩ Resolution ?
❖Real Time Early Warning Bus Fault Detection
❖ Bus Inductance Compensation (94 µH)
❖ Feasibility of 300 µV Threshold ?
Results from Measurements Performed on 27 Oct. at up to 1250 ADC
DQQDC Detector Card now linked up to the WorldFip and LHC Logging
Strong Filtering, Sampling Time 187 ms, 100 points Sliding Average
Post Treatment of Data with Labview
380 µV
1 hour
1250 A
Results from Measurements Performed on 27 Oct.
Voltage during Ramping
4 A/s
1250 A
380 µV
Real Time Noise Floor
Results from Measurements Performed on 27 Oct. at
1250 ADC
Results from Ramping, Flat-Top and Ramp-down
±10 µV
245 ± 45 pΩ / Splice
Results from Measurements Performed on 27 Oct. at 1250 ADC
with DQQDC Detector
~ 1 hour integration / point
100 nV
Zero Closure = 20 nV
3500 Amp Ramp
94 µH
29 October
1 hour
375 µV
4 A/s
Bus Voltage
50 µV
Selected DC Data
7
290 ± 50 pΩ / Splice
Results from Measurements Performed on 29 Oct. at 3500 ADC
with DQQDC Detector
10 min - 1 hour integration / point
200 nV
Zero Closure = 50 nV
8
325 ± 15 pΩ / Splice
Results from Measurements Performed on 30 Oct. at 5000 ADC
with DQQDC Detector
500 nV
Zero Closure = 50 nV
9
Repeatability & Consistency
Same Splice
Different Ramps
Different Days
Ramp [Amp]
1250
3500
5000
mean
Resistance/Splice [pΩ] estimated statistical error
[pΩ]
245
290
325
287
Can we measure better than 1 nΩ ?
YES WE CAN !
45
50
15
28
520 ± 110 pΩ / Splice
Results from Measurements Performed on 30 Oct. at 5000 ADC
with COMPENSATED DQQDC Detector
1 µV
11
335 ± 22 pΩ / Splice
500 nV
Can we measure better than 1 nΩ ?
YES WE CAN !
First Feeble Attempt at Compensation
97% Compensated Signal
4 A/s
Residual = 10 µV out of 400 µV
13
Serious Attempt at Compensation
Uncompensated Bus Signal
Bus Voltage
375 µV
4 A/s
Completely Compensated Bus Signal
±300 µV
PC recapture !
4 A/s
Can we have a detection threshold better than 300 µV ?
YES WE CAN !
Completely Compensated Bus Signal
±20 µV
Can we have a detection threshold better than 300 µV ?
YES WE CAN !
Conclusions from
Preliminary Testing
• Signal noise is amazingly insensitive to cable routing.
– This allows practical routing in the cable trays.
• Barring any unforeseen noise issues, sub nΩ resolution should be possible.
• A 300µV real time early warning threshold is practical.
– But keep in mind that saturation at high field or magnetization at low field may
spoil compensation slightly.
– Some variation in splice resistance must be tolerated.
– Some variation in electronic component noise must be tolerated.
– And many unexplored and hence unforeseen noise sources may spoil and
consume our threshold margin. (TGV, Bastille Day, etc.)
– A healthy margin must be maintained, as false trips may keep the Higgs away.
– Only after operational experience with the entire system will we know if the
threshold really needs to be increased for stability or possibly could be
decreased to provide added security. (The threshold needs to be secure but
flexible.)
YES WE CAN !